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Robust digital output protection

I am working on a digital output concept that I would like to have the following characteristics:
* Output voltage swing: 0 to 5V
* Controllable by the uC from 3.3V power supply
* I would like to be able to switch the output at <100Hz
* I would like output to be current limited to a certain current threshold(assume <200mA)
* I want output resistance from it to be "low"(ie. don't want adding additional resistance in series to limit the current)
* bonus, it would be nice that the output wouldn't budge(get damaged) when stressed a bit with either ESD event of 8kV or +-12V wrong wiring connection(there is another 12 and -12 rail on the unit). Unit doesn't need to function properly in this case, it just can't get damaged.
I currently have something like:
~~![schematic view](https://electrical.codidact.com/uploads/7u73wkmj682invws877itjawa361)~~
In this case V1, powering the digital output, would be current limited through current limit switch set up to 200mA. R2 simulates the ~100mA load.
How would concept for my idea look like?

I am working on a digital output concept that I would like to have the following characteristics:
* Output voltage swing: 0 to 5V
* Controllable by the uC from 3.3V power supply
* I would like to be able to switch the output at <100Hz
* I would like output to be current limited to a certain current threshold (assume <200mA)
* I want output resistance from it to be "low" (ie. don't want adding additional resistance in series to limit the current)
* bonus, it would be nice that the output wouldn't budge (get damaged) when stressed a bit with either ESD event of 8kV or +-12V wrong wiring connection (there is another 12V and -12V rail on the unit). Unit doesn't need to function properly in this case, it just can't get damaged.
I currently have something like:
[![schematic view](https://electrical.codidact.com/uploads/7u73wkmj682invws877itjawa361)](https://electrical.codidact.com/uploads/7u73wkmj682invws877itjawa361)
In this case V1, powering the digital output, would be current limited through current limit switch set up to 200mA. R2 simulates the ~100mA load.
How would concept for my idea look like?

ESD digital-output