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Q&A

Comments on Is Feeding a Watchdog Timer from an ISR a Bad Practice?

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Is Feeding a Watchdog Timer from an ISR a Bad Practice?

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In an embedded system, I require a watchdog to be able to pass ESD qualifications (the main reason for the watchdog requirement is that the device wasn't able to pass the harshest tests of the IEC 61000-4-2 standard). Having no experience with watchdogs, I went through this Memfault article. I liked the events "registration" and "flags" since it easily allows us to do conditional ORing of events depending on the system's state. Plus it feels scalable.

For the feeding part, here's what I put in place:

/** @brief Raise the event flag and feed the watchdog if all required event flags are set.
 *
 *  @param[in] event_flag  Bitmask corresponding to the triggering event.
 */
static void watchdog_feed_if_all_events_set(watchdog_event_t event_flag)
{
    /* Declare as volatile since this function could be called from concurrent ISRs. */
    static volatile watchdog_event_t watchdog_fed_events;

    enter_critical();

    watchdog_fed_events |= event_flag;

    if ((watchdog_fed_events & watchdog_required_events) == watchdog_required_events) {
        bsp_watchdog_feed();
        watchdog_fed_events = 0;
    }
    exit_critical();
}

This function can then be called from any part of the application, including from ISRs.

Now for the question:

I was told it was senseless to feed a watchdog from an ISR and that a redesign is required, but no rationale was provided. I see nothing wrong with my implementation and it works just fine. I feel like a watchdog design is closely related/dependent to the system on which it is implemented and that there are no one-size-fits-all designs.

Am I missing something? Why would someone want to avoid feeding a watchdog from an ISR?

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1 comment thread

"XY problem" about ESD (4 comments)
"XY problem" about ESD
Lundin‭ wrote about 15 hours ago · edited about 14 hours ago

As we discussed before, ESD causing memory corruption or hanging the MCU etc are just symptoms. ESD testing is just as likely to regard a sudden MCU reset by a watchdog or other means as a fail criteria. If possible, I would encourage you to post a separate question here addressing the electronics design and the ESD problem, to solve the root cause.

drkfrx‭ wrote about 14 hours ago

You raise valid points. We'll conduct further investigation, though as of now, we suspect failure of an external IC due to ESD on the SPI line.

Lundin‭ wrote about 14 hours ago · edited about 14 hours ago

drkfrx‭ If you can share the schematics and ideally a photo and/or PCB layout in a separate question, we can help out with troubleshooting that as well. Out of all the failures you can get during EMC testing, ESD problems are relatively easy to spot and fix. Been there done that :)

drkfrx‭ wrote about 14 hours ago

I really appreciate it, but I can hardly disclose the specifics :(

I was told we're aiming for Class B certification, which says system reset are acceptable. Hardware mods would be more costly than patching it with a system watchdog so I guess that only leaves 1 solution.