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Q&A

Comments on Is it allowed to skip a pin to increase creepage distance?

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Is it allowed to skip a pin to increase creepage distance?

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From IEC-62368 for signals below 30kHz the creepage distance for pollution degree 2 and material group IIIa,IIIb (FR-4 boards are IIIa) at 40V is specified to be 1.1mm. We have a connector that has many BGA pads, and the copper-to-copper distance is 0.635mm: Image_alt_text

Putting a slit between is not an option, the only way I could see is to add coating after assembly that would allow to use values for pollution degree 1, which would be 0.16mm, quite a drastic reduction.

One of the engineers mentioned that leaving a pin floating in between also counts towards increasing creepage, but I am not sure about that. The definition of creepage that is used in standard:

Creepage is the shortest path between two conductive parts measured along the surface of a solid insulating material

It would imply that it does not matter if the pin in between is floating or not, but on the other hand, how would the voltage be defined if one of the pins is floating? The voltage could be anything between those two pins! In my mind the pin would have to be physically removed from the connector body for this to be valid, and the pad removed from PCB.

Can anyone comment on the validity of such interpretations of creepage? If you have experience with other standards please share it, IEC is just where I got the numbers from.

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1 comment thread

Standards (1 comment)
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I don't have experience with that particular standard, but do with other standards that also specify clearance and creepage distances, like Intrinsic Safety.

I would be very surprised if just leaving the pin unconnected would allow adding the creepage distances on either side. As you say, you can't guarantee what the voltage on the pin will be. It would be floating, and could pick up stray signals by capacitive coupling, static, etc.

Do you really have a 40 V signal? What voltage does the 0.635 mm distance allow? Can you arrange all signals adjacent to the sensitive one to have a sufficiently low maximum guaranteed voltage difference?

I don't see how you can add a coating after assembly to fix this. The material would have to somehow get between a BGA part and the board it's mounted to, while guaranteeing that all voids are filled. That doesn't sound likely.

I have heard several times from engineers that skipping pin is allowed, but none of them have been able to give a reference or explain how it is compliant. I will see if there are any ways to contact someone from IEC to ask.

It might be easier to talk to someone at whatever place you will have certifying this product. If your company builds these kinds of products regularly, they probably already have an established relationship with a testing house. You are their customer, so they are more likely to talk to you when they have a reasonable expectation of getting the testing/certifying work. They are also the people that will be making the judgement of whether skipping a pin is acceptable according to the standard or not.

Added 17 June 2026

I looked in the Intrinsic Safety standard I have used before to see how it defines clearance and creapage. Here is one of the diagrams and accompanying key:

In this case it does say you can add the creepage on both sides of an unused pin, as long as that pin is "not electrically connected". Maybe your standard has a similar diagram.

History

2 comment threads

Underfill under BGA is an established procedure. (4 comments)
Yes, we do have several signals around 40V. To determine exact voltage 0.635mm allows I would have to... (1 comment)
Underfill under BGA is an established procedure.
Nick Alexeev‭ wrote 3 months ago · edited 3 months ago

Underfill under BGA is an established procedure. The underfill compound is wicked under the BGA by capillary action. Here's a video by Henkel, this too. It got to a point where chip-scale BGAs require underfill just for mechanical robustness.

Skipping 1 deleted comment.

Olin Lathrop‭ wrote 3 months ago

I can understand something wicking into the thin gap between a BGA and the circuit board. However, to be useful in this case, there would have to be a procedure to guarantee no air pockets are caught in the process. If the liquid is applied simultaneously on all 4 sides of the part when it is horizontal, trapped air causing voids seems likely. Does the liquid have to be applied in a certain sequence, orientation, in near-vacuum, etc? How are no voids guaranteed?

Nick Alexeev‭ wrote 3 months ago · edited 3 months ago

Underfill can be applied on one side of the chip and get pulled by capillary tension all the way across. It looks like there’s no method of inspecting underfill for voids which would be compatible with PCB assembly. Here’s a paper which goes through test methods Underfill inspection and testing in SMT (ISSE seminar, 2025). X-ray doesn’t see underfill well enough. The article concludes that each method either doesn’t see underfill, or doesn’t work for PCB assembly because it’s destructive.

Nick Alexeev‭ wrote 3 months ago

I think that O.P.’s idea about coating was to reduce pollution degree, rather than add insulating material between the problematic pins. If the there would be a sealed void, then inside of it would be pollution degree 1, and the required minimum distance would be smaller.