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No, I have not seen this circuit before, and don't know what source you may have gotten it from.

However, I'm not sure that really matters.  I don't know what exactly you are trying to teach, but most likely the derivation of the circuit is the real lesson.  The actual circuit is of little use, and should fall out from deriving it from a shifted-adds multiply.  Granted this circuit is more complicated, but you wouldn't worry about crediting someone for a schematic of 4 resistors around and opamp to make a diff amp, for example.

Note that today this would be a silly way to perform a 4-bit square.  The need for a discrete circuit to do something this specific is minimal to start with, considering that most likely a design with that need would include a microcontroller or FPGA.  Even if it was really needed as a stand-alone circuit for some reason, you'd just use a ROM.  Bits aren't worth what they used to be.

<h2>Circuit derivation</h2>

In general, a 4 x 4 bit multiply can be accomplished with selective shifted ads:

<pre>
                    A3  A2  A1  A0   AND   B0
                A3  A2  A1  A0       AND   B1
            A3  A2  A1  A0           AND   B2
    +   A3  A2  A1  A0               AND   B3
    ------------------------------
    S7  S6  S5  S4  S3  S2  S1  S0
</pre>

The ANDs at right mean that the entire row is ANDed with the indicated bit.  Or you can think of the B bit gates whether its row is included in the sum.

In your case, it's a little simpler since B = A.

The circuit you show is a result of simplifying the above.  For example, we can see immediately that S0 = A0.

Another way of looking at the problem is by exhaustion, since there are only 16 possible cases:

<pre>
 A3 A2 A1 A0  | S7 S6 S5 S4 S3 S2 S1 S0
 -- -- -- --  | -- -- -- -- -- -- -- --
  0  0  0  0  |  0  0  0  0  0  0  0  0
  0  0  0  1  |  0  0  0  0  0  0  0  1
  0  0  1  0  |  0  0  0  0  0  1  0  0
  0  0  1  1  |  0  0  0  0  1  0  0  1
  0  1  0  0  |  0  0  0  1  0  0  0  0
  0  1  0  1  |  0  0  0  1  1  0  0  1
  0  1  1  0  |  0  0  1  0  0  1  0  0
  0  1  1  1  |  0  0  1  1  0  0  0  1
  1  0  0  0  |  0  1  0  0  0  0  0  0
  1  0  0  1  |  0  1  0  1  0  0  0  1
  1  0  1  0  |  0  1  1  0  0  1  0  0
  1  0  1  1  |  0  1  1  1  1  0  0  1
  1  1  0  0  |  1  0  0  1  0  0  0  0
  1  1  0  1  |  1  0  1  0  1  0  0  1
  1  1  1  0  |  1  1  0  0  0  1  0  0
  1  1  1  1  |  1  1  1  0  0  0  0  1
</pre>

From this it is immediately obvious that S1 = 0.

Working from either or both of the representations above, you apply some cranking and eventually reduce the number of adds actually required to end up with your circuit.

Of course other optimizations are also possible.  For example, from the truth table it can be seen that S7 = A3 * A2.  Your circuit doesn't do it that way because it already had an adder for the previous bit with the carry output being exactly S7, so no need to use a separate gate to get S7.  This works if you consider the adders as fundamental building blocks.  That is valid in some implementations.