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Q&A Why is the ACK (acknowledge bit) in the CAN bus frames dominant? What could have been the rationale behind that design decision?

[I’m asking this question out of curiosity. I understand that this aspect of the CAN bus specification is what it is, and can not change.] The ACK bit in any CAN data frame is dominant. Each rece...

2 answers  ·  posted 3y ago by Nick Alexeev‭  ·  last activity 3y ago by Olin Lathrop‭

Question CAN-bus
#2: Post edited by user avatar Nick Alexeev‭ · 2020-10-30T01:59:33Z (over 3 years ago)
  • Why is the ACK (acknowledge bit) in the CAN bus frames dominant? What was the rationale behind this spec?
  • Why is the ACK (acknowledge bit) in the CAN bus frames dominant? What could have been the rationale behind that design decision?
#1: Initial revision by user avatar Nick Alexeev‭ · 2020-10-29T22:35:29Z (over 3 years ago)
Why is the ACK (acknowledge bit) in the CAN bus frames dominant?  What was the rationale behind this spec?
_[I’m asking this question out of curiosity.  I understand that this aspect of the CAN bus specification is what it is, and can not change.]_

The ACK bit in any CAN data frame is dominant.  Each receiving node sets the ACK dominant when it receives a data frame, and doesn’t detect errors.  Dominant ACK acts as a wired NOR.  When the transmitting node sees the ACK in the dominant state, it knows that _at least one other node_ had received the frame without errors.
  
From the ACK bit alone, the transmitting node can’t determine if all nodes have received the message.  From the ACK bit alone, the transmitting node can’t determine if the nodes to whom it may concern have received  the message.

If this ambiguity needs to be resolved, then a higher level protocol which runs on top of CAN should have acknowledge frames.  These would be CAN data frames with acknowledge information.

<h3>Was there another option?</h3>

I think that the other option was to make the ACK bit recessive.  Each receiving node on the bus sets ACK recessive when it receives the data frame, and doesn’t detect errors.  Recessive ACK acts as wired AND.  The sending node sees the recessive ACK and concludes that its message have been sent successfully and every node on the bus had received it.  If one node detects an error, then it drives the ACK bit dominant.  The sender sees the dominant bit, and re-transmits, or takes other measures.