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Ripple doesn't need to be that high. I've done flyback supplies to power isolated sections quite a bit, using a pulse on demand scheme like yours. It's not hard to get the ripple down to ±50 mV. ...

posted 4y ago by Olin Lathrop‭ · edited 4y ago by Olin Lathrop‭

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#2: Post edited by

Olin Lathrop‭ · 2020-12-12T19:02:48Z (almost 4 years ago)

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Ripple doesn't need to be that high. I've done flyback supplies to power isolated sections quite a bit, using a pulse on demand scheme like yours. It's not hard to get the ripple down to ±50 mV. Usually the ripple is within ±100 mV even when you don't do anything special to minimize it.
The real source of ripple with these schemes is usually meta-stability, not the energy from individual pulses. Your circuit will exhibit this, due to the slow feedback, high ESR of the output cap, and poor duty cycle control due to using an evil <strike>666</strike> 555 timer.
Especially if the primary of the transformer runs in continuous mode, there will be meta-stability because it takes a few pulses to wind up and wind down to/from steady state operation. I don't see any evidence in your schematic that you've considered discontinuous versus continuous operation, and certainly none that would appear to address it.
Still, none of that will likely matter in the end. Even if you end up with ±100 mV ripple, so what? As you said, Q4 isn't going to care.
If you want to use a similar topology for powering a CAN transceiver, MCU, and other digital logic, 100 mV ripple may not matter. Look at the power supply requirements of each chip you want to power. A CAN transceiver is probably fine with 5.0±0.1 V. You can add a ferrite "chip inductor" in series followed by a 10 µF cap to ground on each power pin to reduce the high frequencies that the chip may not be able to deal with well.
Occasionally I've needed a relatively clean isolated supply. A common solution I've used is a flyback pulse on demand supply to make the raw voltage, followed by a linear post-regulator. See <a href="https://electrical.codidact.com/articles/277844">this paper</a> where I use the linear post-regulator also as the reference voltage, with the raw voltage regulated to one B-E junction drop above.
The raw supply can be handy for running anything that takes some power but doesn't care much about ripple, like LEDs. Leave the clean post-regulated supply for things that care about ripple and accurate voltage. You can also use the raw supply to feed multiple LDOs that are physically dispersed.
That all said, here are a few comments on your circuit:<ol>
<li>Switching is going to be "slow", due to the opto-isolator, and the fact that the only thing turning off the switch is a pulldown resistor (R6). That may be fine, but don't expect to do PWM at 10s of kHz without a lot of loss.
<li>What's with the 18 V? Does your FET really need that much gate drive? I didn't look it up, but most such FETs are rated for 10 V, and will operate very nicely with 12 V. If so, the higher voltage is just slowing down the switch-off time, and wasting power.
<li>1 mF seems really excessive for the power supply output cap (C2). A lot of capacitance there doesn't do much harm, but that's a lot of space and expense for no apparent gain, not to mention the long term reliability of electrolytic versus ceramic.
Don't just blindly throw a large capacitor at the problem. Do the math. How much energy will be in each pulse? How much capacitance do you need to keep the result of a pulse dumped on the cap to 10 mV, for example? You might be surprised at the answer.
I usually use 10s to maybe 100 µF for the power supply output cap. At most, that's a few ceramics in parallel. Those will be physically much smaller than the behemoth electrolytic you specified, and will have virtually no ESR.
Now consider ESR, and the effect it has on ripple. Figure the current coming out of the diode each pulse, and multiply that by the ESR of the output cap. That causes ripple even with infinite output capacitance. I haven't done the math (that's your job), but my knee jerk reaction is that the ripple caused by the ESR of C2 considerably exceeds that of the pulse energy on its capacitance. Put another way, by using such a large cap, with its accompanying ESR, you are actually making the ripple worse.
<li>Do you really need 7.5 mA thru the LED of OC1 just to have its output pull down the reset line against a 10 kΩ pullup? I didn't look up that opto-coupler, but this seems silly.
~~</ol>~~

Ripple doesn't need to be that high. I've done flyback supplies to power isolated sections quite a bit, using a pulse on demand scheme like yours. It's not hard to get the ripple down to ±50 mV. Usually the ripple is within ±100 mV even when you don't do anything special to minimize it.
The real source of ripple with these schemes is usually meta-stability, not the energy from individual pulses. Your circuit will exhibit this, due to the slow feedback, high ESR of the output cap, and poor duty cycle control due to using an evil <strike>666</strike> 555 timer.
Especially if the primary of the transformer runs in continuous mode, there will be meta-stability because it takes a few pulses to wind up and wind down to/from steady state operation. I don't see any evidence in your schematic that you've considered discontinuous versus continuous operation, and certainly none that would appear to address it.
Still, none of that will likely matter in the end. Even if you end up with ±100 mV ripple, so what? As you said, Q4 isn't going to care.
If you want to use a similar topology for powering a CAN transceiver, MCU, and other digital logic, 100 mV ripple may not matter. Look at the power supply requirements of each chip you want to power. A CAN transceiver is probably fine with 5.0±0.1 V. You can add a ferrite "chip inductor" in series followed by a 10 µF cap to ground on each power pin to reduce the high frequencies that the chip may not be able to deal with well.
Occasionally I've needed a relatively clean isolated supply. A common solution I've used is a flyback pulse on demand supply to make the raw voltage, followed by a linear post-regulator. See <a href="https://electrical.codidact.com/articles/277844">this paper</a> where I use the linear post-regulator also as the reference voltage, with the raw voltage regulated to one B-E junction drop above.
The raw supply can be handy for running anything that takes some power but doesn't care much about ripple, like LEDs. Leave the clean post-regulated supply for things that care about ripple and accurate voltage. You can also use the raw supply to feed multiple LDOs that are physically dispersed.
That all said, here are a few comments on your circuit:<ol>
<li>Switching is going to be "slow", due to the opto-isolator, and the fact that the only thing turning off the switch is a pulldown resistor (R6). That may be fine, but don't expect to do PWM at 10s of kHz without a lot of loss.
<li>What's with the 18 V? Does your FET really need that much gate drive? I didn't look it up, but most such FETs are rated for 10 V, and will operate very nicely with 12 V. If so, the higher voltage is just slowing down the switch-off time, and wasting power.
<li>1 mF seems really excessive for the power supply output cap (C2). A lot of capacitance there doesn't do much harm, but that's a lot of space and expense for no apparent gain, not to mention the long term reliability of electrolytic versus ceramic.
Don't just blindly throw a large capacitor at the problem. Do the math. How much energy will be in each pulse? How much capacitance do you need to keep the result of a pulse dumped on the cap to 10 mV, for example? You might be surprised at the answer.
I usually use 10s to maybe 100 µF for the power supply output cap. At most, that's a few ceramics in parallel. Those will be physically much smaller than the behemoth electrolytic you specified, and will have virtually no ESR.
Now consider ESR, and the effect it has on ripple. Figure the current coming out of the diode each pulse, and multiply that by the ESR of the output cap. That causes ripple even with infinite output capacitance. I haven't done the math (that's your job), but my knee jerk reaction is that the ripple caused by the ESR of C2 considerably exceeds that of the pulse energy on its capacitance. Put another way, by using such a large cap, with its accompanying ESR, you are actually making the ripple worse.
<li>Do you really need 7.5 mA thru the LED of OC1 just to have its output pull down the reset line against a 10 kΩ pullup? I didn't look up that opto-coupler, but this seems silly.
</ol>
<hr>
<blockquote>Let's try to dig in some math. 100kHz of fsw would give 5us of ON time which will end up being 12V/475uH = 25kA/s on the primary of L1(126mA on 5us period). Q1 could easily grasp this without getting hot and it's well within the limits of L1.
On the secondary side, this would end up being 20.4V/1.3mH=15.7kA/s=80mA</blockquote>
You're looking at the wrong thing to determine ripple from a switching pulse. It has nothing to do with Q4 at all. It's only about how much the voltage on C2 goes up as a result of each switching pulse.
The new information you provided is that the primary of the transformer is 475 µH. You seem to be saying that the switch will be driven by a 100 kHz square wave, so 5 µs on time and 5 µs off time. Let's further assume (for now) that this is just at the edge of continuous mode. In other words, the primary current starts at 0 each pulse, and the secondary current goes to 0 just at the end of the off time.
At the end of the on time, the current in the primary is:
    (12 V)(5 µs)/(475 µH) = 126 mA
That agrees with what you got. However, the only relevant part of that is what the total energy in the inductor is now. That's:
    (126 mA)2(475 µH)/2 = 3.8 µJ
With the simplifying assumption of no losses, all that is going to end up on C2 one way or another. The exact voltage, current, and time don't matter.
The question is then how much will the voltage of C2 go up when it is already at 18.7 V and another 3.8 µJ get dumped on it. Instead of solving for the capacitance given some voltage increase, I'll pick a plausible (but low by gut feeling) capacitance of 10 µF and see what that does. Since the ripple will scale inversely with that capacitance, it will be easy to see what the ripple will be with other values.
With C2 of 10 µF, and with 18.7 V on it, it's total energy is:
    (10 µF)(18.7 V)2/2 = 1.75 mJ
Adding 3.8 µJ to that will make the voltage go up by the square root of the ratio of 1.7538 to 1.7500 J.
    sqrt(1.7538 / 1.7500)⋅(18.7 V) = 18.7203 V
for a rise of 20.3 mV. That's the ripple from a single switching pulse with 10 µF capacitance. So roughly 10 µF gets you 20 mV ripple.
I'd want at least 20 real µF so that the per-pulse ripple is 10 mV or less. 10 µF 35 V ceramic caps are readily available. But, look at how much the capacitance tails off at high voltages. Three of them may be needed to guarantee at least 20 µF at 19 V. Still, that's a lot better than a big fat 1 mF electrolytic, has much less ESR, and can handle much higher temperature with much longer lifetime.
That all sounds rosy, but there's more too it. As I said before, your control scheme will almost certainly go meta-stable. Ripple due to individual pulses isn't really the issue. The ripple will likely be ±50 to ±100 mV. It will also be inversely proportional to the output capacitance, so I'd want C2 to be a bit bigger. Maybe a couple of 22 µF 25 V caps would be good.
It should be obvious that the energy slugs needed to drive the gate of Q4 are irrelevant in comparison, but let's look into that in case someone is watching and wonders why it's left out.
A quick way to see that driving Q4 doesn't matter is just by comparing the total gate capacitance to the capacitance on the supply. You say the gate is 3.3 nF. That's 0.083% of C2 at 40 µF. Instantly connecting a discharged 3.3 nF to 40 µF at 19 V will only cause a 1.6 mV drop. Again, the actual current and time are irrelevant for this analysis.

#1: Initial revision by

Olin Lathrop‭ · 2020-12-11T14:56:22Z (almost 4 years ago)

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Ripple doesn't need to be that high. I've done flyback supplies to power isolated sections quite a bit, using a pulse on demand scheme like yours. It's not hard to get the ripple down to &plusmn;50 mV. Usually the ripple is within &plusmn;100 mV even when you don't do anything special to minimize it.

The real source of ripple with these schemes is usually meta-stability, not the energy from individual pulses. Your circuit will exhibit this, due to the slow feedback, high ESR of the output cap, and poor duty cycle control due to using an evil <strike>666</strike> 555 timer.

Especially if the primary of the transformer runs in continuous mode, there will be meta-stability because it takes a few pulses to wind up and wind down to/from steady state operation. I don't see any evidence in your schematic that you've considered discontinuous versus continuous operation, and certainly none that would appear to address it.

Still, none of that will likely matter in the end. Even if you end up with &plusmn;100 mV ripple, so what? As you said, Q4 isn't going to care.

If you want to use a similar topology for powering a CAN transceiver, MCU, and other digital logic, 100 mV ripple may not matter. Look at the power supply requirements of each chip you want to power. A CAN transceiver is probably fine with 5.0&plusmn;0.1 V. You can add a ferrite "chip inductor" in series followed by a 10 &micro;F cap to ground on each power pin to reduce the high frequencies that the chip may not be able to deal with well.

Occasionally I've needed a relatively clean isolated supply. A common solution I've used is a flyback pulse on demand supply to make the raw voltage, followed by a linear post-regulator. See <a href="https://electrical.codidact.com/articles/277844">this paper</a> where I use the linear post-regulator also as the reference voltage, with the raw voltage regulated to one B-E junction drop above.

The raw supply can be handy for running anything that takes some power but doesn't care much about ripple, like LEDs. Leave the clean post-regulated supply for things that care about ripple and accurate voltage. You can also use the raw supply to feed multiple LDOs that are physically dispersed.

That all said, here are a few comments on your circuit:<ol>

<li>Switching is going to be "slow", due to the opto-isolator, and the fact that the only thing turning off the switch is a pulldown resistor (R6). That may be fine, but don't expect to do PWM at 10s of kHz without a lot of loss.

<li>What's with the 18 V? Does your FET really need that much gate drive? I didn't look it up, but most such FETs are rated for 10 V, and will operate very nicely with 12 V. If so, the higher voltage is just slowing down the switch-off time, and wasting power.

<li>1 mF seems really excessive for the power supply output cap (C2). A lot of capacitance there doesn't do much harm, but that's a lot of space and expense for no apparent gain, not to mention the long term reliability of electrolytic versus ceramic.

Don't just blindly throw a large capacitor at the problem. Do the math. How much energy will be in each pulse? How much capacitance do you need to keep the result of a pulse dumped on the cap to 10 mV, for example? You might be surprised at the answer.

I usually use 10s to maybe 100 &micro;F for the power supply output cap. At most, that's a few ceramics in parallel. Those will be physically much smaller than the behemoth electrolytic you specified, and will have virtually no ESR.

Now consider ESR, and the effect it has on ripple. Figure the current coming out of the diode each pulse, and multiply that by the ESR of the output cap. That causes ripple even with infinite output capacitance. I haven't done the math (that's your job), but my knee jerk reaction is that the ripple caused by the ESR of C2 considerably exceeds that of the pulse energy on its capacitance. Put another way, by using such a large cap, with its accompanying ESR, you are actually making the ripple worse.

<li>Do you really need 7.5 mA thru the LED of OC1 just to have its output pull down the reset line against a 10 k&Omega; pullup? I didn't look up that opto-coupler, but this seems silly.

</ol>

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