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Q&A Is it possible to design an n-bit full adder using SystemVerilog?

module full_adder #(parameter WIDTH = 4) (input logic [WIDTH - 1: 0] a, b, input logic carry_in, output logic carry_out, output logic [WIDTH - 1: ...

posted 4y ago by System‭ · edited 4y ago by System‭

Answer

#3: Post edited by (deleted user) · 2021-02-23T13:20:15Z (almost 4 years ago)

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```
module full_adder
#(parameter WIDTH = 4)
(input logic [WIDTH - 1: 0] a,
b,
input logic carry_in,
output logic carry_out,
output logic [WIDTH - 1: 0] sum);
assign {carry_out, sum} = a + b + carry_in;
endmodule
```
~~The above design is fully parameterised. Full adders of any positive integral widths can be obtained by changing the value of the `WIDTH` parameter.~~

```
module full_adder
#(parameter WIDTH = 4)
(input logic [WIDTH - 1: 0] a,
b,
input logic carry_in,
output logic carry_out,
output logic [WIDTH - 1: 0] sum);
assign {carry_out, sum} = a + b + carry_in;
endmodule
```
The above design is parameterised, so full adders of any positive integral widths can be obtained by changing the value of the `WIDTH` parameter.

#2: Post edited by (deleted user) · 2021-02-23T13:00:01Z (almost 4 years ago)

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```
module full_adder
#(parameter WIDTH = 4)
(input logic [WIDTH - 1: 0] a,
b,
input logic carry_in,
output logic carry_out,
output logic [WIDTH - 1: 0] sum);
~~assign {carry_out, sum} = a + b;~~
endmodule
```
The above design is fully parameterised. Full adders of any positive integral widths can be obtained by changing the value of the `WIDTH` parameter.

```
module full_adder
#(parameter WIDTH = 4)
(input logic [WIDTH - 1: 0] a,
b,
input logic carry_in,
output logic carry_out,
output logic [WIDTH - 1: 0] sum);
assign {carry_out, sum} = a + b + carry_in;
endmodule
```
The above design is fully parameterised. Full adders of any positive integral widths can be obtained by changing the value of the `WIDTH` parameter.

#1: Initial revision by (deleted user) · 2021-02-23T12:51:02Z (almost 4 years ago)

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```
module full_adder
  #(parameter WIDTH = 4)
  (input logic [WIDTH - 1: 0] a, 
                              b, 
   input logic carry_in,
   output logic carry_out,
   output logic [WIDTH - 1: 0] sum);

assign {carry_out, sum} = a + b;

endmodule
```
The above design is fully parameterised. Full adders of any positive integral widths can be obtained by changing the value of the `WIDTH` parameter.

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