To be clear and protect against possible future edits, here is the circuit being discussed:
As you say, this is a differential to single ended converter. In this case, the MOSFETs have likely been optimized so that they act as voltage-controlled current sources over most of their range. They also need to be well matched. This circuit is rather unsuitable for discrete MOSFETs out of a bin, but can be quite acceptable in an IC. In that case, the matching between parts will be good (same section of the same wafer), and the parameters can be adjusted for a large current source range.
Q1 sinks current proportional to the positive input voltage. Actually the function of voltage to current may not be all that linear, but the important part is that Q2 has close to the same function.
Q3 and Q4 form a current mirror. The gate voltage on Q3 automatically adjusts itself to whatever it takes to allow its drain current to pass. In that sense, it becomes a current to voltage converter. The presumption is that Q4 has the same characteristics as Q3. Since the same gate voltage drives both transistors, both will allow the same current to pass.
The net effect of Q3 and Q4 is that whatever current Q1 sinks, that same amount is sourced onto the drain of Q2.
Now we have two current sources connected together. Note that these are only passive current sources. They allow the desired current to pass as long as sufficient voltage is applied. Another way to think of it is as if each current sources is a controlled variable resistance. The resistance is internally adjusted to allow the desired current to pass. Current can't be created by these current sources. At most they can make their internal resistance 0. Of course real FETs don't go all the way to 0, and only work as a current source over some voltage and current range, but that can be ignored for now until the circuit is understood. After that, it would be good to look at the FET specs and see over what ranges of voltage and current they will operate as required by this circuit.
So now we have Q4 and Q2 acting like passive current sources in series. Remember that the current Q4 tries to source is roughly proportional to the positive input voltage, and the current Q2 tries to sink is the same function of the negative input voltage.
Even a slight imbalance in the two desired currents will cause a significant voltage offset. When the positive input is higher than the negative input, then Q4 wants to pass more current than Q2. The result is the voltage goes high. The same thing happens in reverse when the negative input is greater than the positive input.