Unterminated SPI bus needs expansion board to work properly
I'm supporting a piece of legacy hardware that routes the SPI bus through a set of headers to an expansion board. Since the expansion board doesn't actually use the SPI bus, we simply ignored the incoming SPI lines when we revised the expansion board.
However, we are now experiencing seemingly random errors on the SPI bus, as it communicates with two devices on the main board. Since there is no source or end termination present on the SPI bus, it makes me wonder if the extra capacitance of the expansion board was enough to prevent reflections.
The main board will not be revised for some time, so I would like to figure out what modification (extra capacitance? resistance?) I could make to the expansion boards that would help prevent SPI reflections, or if there are other possibilities that I'm not thinking of.
I should also mention that this is a low-power, battery-operated system. The top speed for SPI communication on this board is about 1MHz.
It seems like a similar question to this: https://electronics.stackexchange.com/questions/33372/spi-bus-termination-considerations
1 answer
The following users marked this post as Works for me:
| User | Comment | Date |
|---|---|---|
| TimH | (no comment) | Feb 21, 2023 at 00:39 |
At 1 MHz it's probably not transmission line effects.
It's not clear from your question whether the SPI bus works on the main board with the expansion board connected, but not when it's not connected. If so, I expect you're right about the additional capacitance. An easy way to check this is to add a little deliberate capacitance on each SPI line to ground. Perhaps you can do this with an expansion board connector that only has the caps and doesn't connect to any expansion board. Or solder two caps to the bottom of the expansion connector pins.
I'd start with 100 pF caps. If your SPI drivers have 100 Ω output impedance, that's a time constant of 10 ns. 95% settling requires 3 time constants, so 30 ns. You say the SPI bus is running at 1 MHz, so 500 ns levels. 30 ns is a small time compared to that.
If adding deliberate caps instead of the expansion board does make the SPI more robust, then it would be good to understand why. Again, I expect it's not transmission line reflections, especially since it gets better when you make the lines longer. My guess is crosstalk. Capacitance on the lines lowers their impedance at high frequencies, reducing the noise from capacitively coupled edges.
Still, this shouldn't be happening on a reasonably designed circuit board. I suspect the real problem is bad layout. Do you have a board-wide ground plane? Do all ICs have bypass caps between their power and ground pins, physically close to those ICs? Are the SPI lines straight within reason? I expect that after some investigation you'll find the answer to one or more of these questions to be "no".
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