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Q&A SDR SDRAM PCB Timing Budget

It would help to provide links in your question to the datasheets. Without the datasheets I can only give general advice. Look a the memory datasheet and see what the setup and hold time requirem...

posted 11mo ago by Olin Lathrop‭

Answer
#1: Initial revision by user avatar Olin Lathrop‭ · 2023-05-26T14:08:56Z (11 months ago)
It would help to provide links in your question to the datasheets.

Without the datasheets I can only give general advice.  Look a the memory datasheet and see what the setup and hold time requirements are.  There is always a window of time around a clock edge where the data must be held steady on a write.  This is the window that you have to guarantee will always be met <i>at the chip pins</i>.

Look at the reverse specifications for reading from the memory.  Now the micro has minimum setup and hold time requirements.

Now look at what the microcontroller says the minimum guaranteed setup and hold times are relative to whatever clock edge it produces.  Hopefully there is both more setup and more hold time that what the memory chip requires.  If not, then it gets tricky because the clock needs to be skewed relative to the data.

Even more hopefully, the total setup+hold time out of the micro exceeds the minimum setup+hold required by the memory chip.  If not, then the two can't be connected directly no matter how the clock is skewed relative to the data.  You will need some external flip-flops or the like.  That gets messy.  Normally you'd use a memory chip that is compatible with the particular micro.  Let's proceed assuming that is the case and the two can be connected directly.

Let's also assume that setup and hold time out of the micro (and the other direction for reading) both exceed the minimum requirement of the memory.  That means you can directly connect the two, assuming a perfect connection.  You also need to look at how much extra setup and hold time there is.  That tells you how much skew you can tolerate between the clock and any data line.

No connection is perfect.  When you're looking at individual nanoseconds, then every PCB trace is a delay line.  The speed of light in vacuum is 300 mm/ns, or 11.8 inches/ns.  That's a "long" distance for a PCB trace, especially when you've carefully placed the micro and memory next to each other.  However, signals on PCB traces propagate slower than the speed of light.  The exact speed depends on the capacitance to the ground plane, inductance of the traces, and properties of the dielectric.

This is where you should get some data from your PCB fab house.  They should be able to give you some guidance on this, particularly the distance between different layers.  Most of the other parameters will be reasonably similar between boards from different vendors.  An 8 mil wide trace in a "1 ounce" copper layer is going to be pretty much the same thing regardless of who makes the board.  Most places will use FR-4 fiberglass, although you can't leave that to chance when you care about propagation delay at this level.  The main variable will be distances between layers, which affects capacitance to the ground plane, which affects propagation speed.

While you need to have some idea how much each trace will delay, what you really try to do is to match the delay between traces.  You also need a solid ground plane in the next layer under where these traces will be, otherwise the delay will be unpredictable.  You have to think of these traces being transmission lines, so the ground plane is an integral part of getting the signals from one end to the other.

Some memories use differential signals.  In that case the transmission line is between the two signals, not with the ground plane.  In that case you have to keep the two signals next to each other to keep the impedance of the transmission line reasonably constant.

In most cases, you place the chips close to each other, then route the data and clock traces so that they all have the same length.  Avoid sharp turns since those add inductance and therefore more delay than the same length of trace in a straight line.

Again, it would be good to know how much time skew you have to work with.  If you can afford up to 10 ns of skew, then you place the parts close to each other and things will be fine as long as the routing isn't ridiculous.  If individual nanoseconds matter, then you have to pay attention to this carefully.

Also, don't forget termination of the transmission line.  With differential signalling, the chips are usually designed to assume termination at each end.  With single-ended signals you have to look carefully at the drive capability to see whether the drivers can tolerate the characteristic impedance.  It gets tricky.