Post History

The other answers are excellent justification to the the industry standards imposed on CMOS logic.  The historical migration to smaller lithography CMOS led to lower Cds values which led to faster rise times or higher toggle f's. However realize that the standard has been undocumented standards of 50 ohms then 25 ohms at nominal voltage for reductions from 5V to all the lower threshold logic families. Naturally Rdson  lowers with rising Vdd and 10% Vdd yields a wide variation in RdsOn or Vol/Iol=Rs.

3.3V was more of arbitrary 2/3 of the 5V standard. But if if you choose a lower Vdd like 3V in a 3.3 V family the RdsOn is slightly higher and the Pd is slightly lower for a given fmax and the risetime is slightly higher with the lower drive current.

I hope this satisfies your curiosity.