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One common solution for some 3 LDO's is to use a Buck regulator followed by a very low dropout PFET linear regulator combined into one part. IC's with very low V logic-level FETs (Vt=0.65) are used...
Answer
#3: Post edited
by
TonyStewart
·
2024-08-06T00:51:51Z (3 months ago)
One common solution for some 3 LDO's is to use a Buck regulator followed by a very low dropout PFET linear regulator combined into one part. IC's with very low V logic-level FETs (Vt=0.65) are used in a 1.2V supply. Low noise is preferred for Vref on ADCs used by some uC's.- The voltage ratio (%Vo/Vin) is a good estimate of the efficiency for LDO's except for some minimum load current required.
- The choice comes down to your specs for; cost, complexity, efficiency and ripple. Low ripple SMPS demand the utmost care in following design guidelines from the OEM for BOM selection, cooling and power layout.
- One common solution for some 3 LDO's is to use a Buck regulator followed by a very low dropout PFET linear regulator combined into one part. IC's with very low V logic-level FETs (Vt=0.65) are used in a 1.2V supply. Low noise is preferred for Vref and Va on ADCs used by some uC's.
- The voltage ratio (%Vo/Vin) is a good estimate of the efficiency for LDO's except for some minimum load current required.
- The choice comes down to your specs for; cost, complexity, efficiency and ripple. Low ripple SMPS demand the utmost care in following design guidelines from the OEM for BOM selection, cooling and power layout.
#2: Post edited
by
TonyStewart
·
2024-08-06T00:51:30Z (3 months ago)
One common solution for some 3 LDO's is to use a Buck regulator followed by a very low dropout PFET linear regulator combined into one part. Using very low logic level FETs (Vt=0.65) for a 1.2V supply. Low noise is preferred for Vref on ADCs used by some uC's.- The voltage ratio (%Vo/Vin) is a good estimate of the efficiency for LDO's except for some minimum load current required.
- The choice comes down to your specs for; cost, complexity, efficiency and ripple. Low ripple SMPS demand the utmost care in following design guidelines from the OEM for BOM selection, cooling and power layout.
- One common solution for some 3 LDO's is to use a Buck regulator followed by a very low dropout PFET linear regulator combined into one part. IC's with very low V logic-level FETs (Vt=0.65) are used in a 1.2V supply. Low noise is preferred for Vref on ADCs used by some uC's.
- The voltage ratio (%Vo/Vin) is a good estimate of the efficiency for LDO's except for some minimum load current required.
- The choice comes down to your specs for; cost, complexity, efficiency and ripple. Low ripple SMPS demand the utmost care in following design guidelines from the OEM for BOM selection, cooling and power layout.
#1: Initial revision
by
TonyStewart
·
2024-08-06T00:50:09Z (3 months ago)
One common solution for some 3 LDO's is to use a Buck regulator followed by a very low dropout PFET linear regulator combined into one part. Using very low logic level FETs (Vt=0.65) for a 1.2V supply. Low noise is preferred for Vref on ADCs used by some uC's. The voltage ratio (%Vo/Vin) is a good estimate of the efficiency for LDO's except for some minimum load current required. The choice comes down to your specs for; cost, complexity, efficiency and ripple. Low ripple SMPS demand the utmost care in following design guidelines from the OEM for BOM selection, cooling and power layout.