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I'm trying to implement a circuit I read about in a book recently, but having a hard time deriving the relationships for the required impedances for error corrector balance. Here is the circuit: ...
#3: Post edited
by
Nick Alexeev
·
2024-08-19T15:07:13Z (3 months ago)
Having a hard time understanding discrete audio amplifier output stage error corrector circuit, any thoughts?
- Having a hard time understanding discrete audio amplifier output stage error corrector circuit
Edit: I have been informed on stackoverflow that "any thoughts" isn't a valid question about electronics.... if this is an issue, my apologies and please let me know if I need to condense my question further.- I'm trying to implement a circuit I read about in a book recently, but having a hard time deriving the relationships for the required impedances for error corrector balance.
- Here is the circuit:
- 
- - The amplifier second stage (VAS) drives the output stage through dr+
- and dr-
- - The error corrector circuit entails Q5,10,11,6 and
- R1,2,3,4,5.
- - From what I've managed to understand from the book, this
- is essentially a unity gain diff amp, where the node "fb" (which
- contains all base current nonlinearities and voltage gain errors) is
- compared against the VAS signal, and then the difference is
- subtracted through R4/5 as a current.
- I've been having a hard time figuring out what design rules / considerations, and thought I would ask here to see if anyone had any ideas / suggestions:
- - R1/R2: the book mentions that it might be helpful to "attenuate the error signal" through R1/R2. My assumptions for R1 is that it needs to be higher impedance than say, 200 ohms, as to load down the output stage as little as possible. I am lost on what the purpose of R2 is. Equal current sharing?
- - R3: the book states that R3 limits transconductance of Q11/6. This makes sense to me as it would contribute to the gm of either transistor equally, and maybe it's functioning as a summing node for the emitter currents of Q11/6? My guess with R3 is that it needs to small/small-ish.
- - Q3/Q4: I believe these transistors provide a high impedance input to the VAS signal, and a low impedance output to the drivers for the output transistors. Also, I think that they act as the injection point for the error signal through R4/5.
- - R4/5: this is where I'm completely lost. The book states that R4/5 act as the method for adding the error signal back into the VAS signal, effectively cancelling out the output stage error. My best guess with R4/5 is that there is some expression that involves the gm of Q11/6 to scale the output current proportionally to achieve corrector balance through some arithmetic combination of the current through R4/5 and its respective pre-driver transistor (Q3/4).
These are the ideas I've been having. If anything else comes to mind I'll try to edit the post, but would appreciate any ideas/discourse as I haven't been making much progress with my attempted analysis.Thanks!
- I'm trying to implement a circuit I read about in a book recently, but having a hard time deriving the relationships for the required impedances for error corrector balance.
- Here is the circuit:
- 
- - The amplifier second stage (VAS) drives the output stage through dr+
- and dr-
- - The error corrector circuit entails Q5,10,11,6 and
- R1,2,3,4,5.
- - From what I've managed to understand from the book, this
- is essentially a unity gain diff amp, where the node "fb" (which
- contains all base current nonlinearities and voltage gain errors) is
- compared against the VAS signal, and then the difference is
- subtracted through R4/5 as a current.
- I've been having a hard time figuring out what design rules / considerations, and thought I would ask here to see if anyone had any ideas / suggestions:
- - R1/R2: the book mentions that it might be helpful to "attenuate the error signal" through R1/R2. My assumptions for R1 is that it needs to be higher impedance than say, 200 ohms, as to load down the output stage as little as possible. I am lost on what the purpose of R2 is. Equal current sharing?
- - R3: the book states that R3 limits transconductance of Q11/6. This makes sense to me as it would contribute to the gm of either transistor equally, and maybe it's functioning as a summing node for the emitter currents of Q11/6? My guess with R3 is that it needs to small/small-ish.
- - Q3/Q4: I believe these transistors provide a high impedance input to the VAS signal, and a low impedance output to the drivers for the output transistors. Also, I think that they act as the injection point for the error signal through R4/5.
- - R4/5: this is where I'm completely lost. The book states that R4/5 act as the method for adding the error signal back into the VAS signal, effectively cancelling out the output stage error. My best guess with R4/5 is that there is some expression that involves the gm of Q11/6 to scale the output current proportionally to achieve corrector balance through some arithmetic combination of the current through R4/5 and its respective pre-driver transistor (Q3/4).
- These are the ideas I've been having. If anything else comes to mind I'll try to edit the post, but would appreciate any ideas/discourse as I haven't been making much progress with my attempted analysis.
#2: Post edited
by
drinkingcube
·
2024-08-19T04:45:45Z (3 months ago)
- I'm trying to implement a circuit I read about in a book recently, but having a hard time deriving the relationships for the required impedances for error corrector balance.
- Here is the circuit:
- 
- - The amplifier second stage (VAS) drives the output stage through dr+
- and dr-
- - The error corrector circuit entails Q5,10,11,6 and
- R1,2,3,4,5.
- - From what I've managed to understand from the book, this
- is essentially a unity gain diff amp, where the node "fb" (which
- contains all base current nonlinearities and voltage gain errors) is
- compared against the VAS signal, and then the difference is
- subtracted through R4/5 as a current.
- I've been having a hard time figuring out what design rules / considerations, and thought I would ask here to see if anyone had any ideas / suggestions:
- - R1/R2: the book mentions that it might be helpful to "attenuate the error signal" through R1/R2. My assumptions for R1 is that it needs to be higher impedance than say, 200 ohms, as to load down the output stage as little as possible. I am lost on what the purpose of R2 is. Equal current sharing?
- - R3: the book states that R3 limits transconductance of Q11/6. This makes sense to me as it would contribute to the gm of either transistor equally, and maybe it's functioning as a summing node for the emitter currents of Q11/6? My guess with R3 is that it needs to small/small-ish.
- - Q3/Q4: I believe these transistors provide a high impedance input to the VAS signal, and a low impedance output to the drivers for the output transistors. Also, I think that they act as the injection point for the error signal through R4/5.
- - R4/5: this is where I'm completely lost. The book states that R4/5 act as the method for adding the error signal back into the VAS signal, effectively cancelling out the output stage error. My best guess with R4/5 is that there is some expression that involves the gm of Q11/6 to scale the output current proportionally to achieve corrector balance through some arithmetic combination of the current through R4/5 and its respective pre-driver transistor (Q3/4).
- These are the ideas I've been having. If anything else comes to mind I'll try to edit the post, but would appreciate any ideas/discourse as I haven't been making much progress with my attempted analysis.
- Thanks!
- Edit: I have been informed on stackoverflow that "any thoughts" isn't a valid question about electronics.... if this is an issue, my apologies and please let me know if I need to condense my question further.
- I'm trying to implement a circuit I read about in a book recently, but having a hard time deriving the relationships for the required impedances for error corrector balance.
- Here is the circuit:
- 
- - The amplifier second stage (VAS) drives the output stage through dr+
- and dr-
- - The error corrector circuit entails Q5,10,11,6 and
- R1,2,3,4,5.
- - From what I've managed to understand from the book, this
- is essentially a unity gain diff amp, where the node "fb" (which
- contains all base current nonlinearities and voltage gain errors) is
- compared against the VAS signal, and then the difference is
- subtracted through R4/5 as a current.
- I've been having a hard time figuring out what design rules / considerations, and thought I would ask here to see if anyone had any ideas / suggestions:
- - R1/R2: the book mentions that it might be helpful to "attenuate the error signal" through R1/R2. My assumptions for R1 is that it needs to be higher impedance than say, 200 ohms, as to load down the output stage as little as possible. I am lost on what the purpose of R2 is. Equal current sharing?
- - R3: the book states that R3 limits transconductance of Q11/6. This makes sense to me as it would contribute to the gm of either transistor equally, and maybe it's functioning as a summing node for the emitter currents of Q11/6? My guess with R3 is that it needs to small/small-ish.
- - Q3/Q4: I believe these transistors provide a high impedance input to the VAS signal, and a low impedance output to the drivers for the output transistors. Also, I think that they act as the injection point for the error signal through R4/5.
- - R4/5: this is where I'm completely lost. The book states that R4/5 act as the method for adding the error signal back into the VAS signal, effectively cancelling out the output stage error. My best guess with R4/5 is that there is some expression that involves the gm of Q11/6 to scale the output current proportionally to achieve corrector balance through some arithmetic combination of the current through R4/5 and its respective pre-driver transistor (Q3/4).
- These are the ideas I've been having. If anything else comes to mind I'll try to edit the post, but would appreciate any ideas/discourse as I haven't been making much progress with my attempted analysis.
- Thanks!
#1: Initial revision
by
drinkingcube
·
2024-08-19T03:53:31Z (3 months ago)
Having a hard time understanding discrete audio amplifier output stage error corrector circuit, any thoughts?
I'm trying to implement a circuit I read about in a book recently, but having a hard time deriving the relationships for the required impedances for error corrector balance. Here is the circuit:  - The amplifier second stage (VAS) drives the output stage through dr+ and dr- - The error corrector circuit entails Q5,10,11,6 and R1,2,3,4,5. - From what I've managed to understand from the book, this is essentially a unity gain diff amp, where the node "fb" (which contains all base current nonlinearities and voltage gain errors) is compared against the VAS signal, and then the difference is subtracted through R4/5 as a current. I've been having a hard time figuring out what design rules / considerations, and thought I would ask here to see if anyone had any ideas / suggestions: - R1/R2: the book mentions that it might be helpful to "attenuate the error signal" through R1/R2. My assumptions for R1 is that it needs to be higher impedance than say, 200 ohms, as to load down the output stage as little as possible. I am lost on what the purpose of R2 is. Equal current sharing? - R3: the book states that R3 limits transconductance of Q11/6. This makes sense to me as it would contribute to the gm of either transistor equally, and maybe it's functioning as a summing node for the emitter currents of Q11/6? My guess with R3 is that it needs to small/small-ish. - Q3/Q4: I believe these transistors provide a high impedance input to the VAS signal, and a low impedance output to the drivers for the output transistors. Also, I think that they act as the injection point for the error signal through R4/5. - R4/5: this is where I'm completely lost. The book states that R4/5 act as the method for adding the error signal back into the VAS signal, effectively cancelling out the output stage error. My best guess with R4/5 is that there is some expression that involves the gm of Q11/6 to scale the output current proportionally to achieve corrector balance through some arithmetic combination of the current through R4/5 and its respective pre-driver transistor (Q3/4). These are the ideas I've been having. If anything else comes to mind I'll try to edit the post, but would appreciate any ideas/discourse as I haven't been making much progress with my attempted analysis. Thanks!