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If so, how would that work without a source resistor? Quite well actually. If you look at the 2SK1109 you'll see that it has this characteristic: - I've highlighted the zero voltage bias po...
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#5: Post edited
by
Andy aka
·
2024-10-26T11:11:45Z (6 days ago)
- > _If so, how would that work without a source resistor?_
- Quite well actually. If you look at the [2SK1109](https://www.renesas.com/en/document/dst/2sk1109-data-sheet) you'll see that it has this characteristic: -
- 
- I've highlighted the zero voltage bias point with a red rectangle. This is the situation you get when there is no source resistor. The drain current is about 60 to 75 μA over a range of drain voltages from 1 volt to 10 volts and, of course, if you have a signal on your gate, it will "modulate" the drain current up and down and this will be seen as a voltage waveform across the external drain pull-up resistor.
- This JFET is particularly suited to electret capsules because it only consumes tens to hundreds of microamps when quiescent. That as a specification is called \$I_{DSS}\$ and you want it to be generally sub 1 mA or you are just wasting power (especially important for battery applications).
- _What circuit voltage gain will you get with a 1 kΩ drain resistor?_
- The data sheet says that the forward transconductance is 1000 μS <-- that 1000 micro-siemens in case you thought it said micro-seconds. That is equivalent to 1 μA per millivolt meaning if you move the gate up and down a mV then the drain current is moved up and down by 1 μA. Into a 1 kΩ drain resistor that's a signal level of +/-1 mV.
You might say at this point that the voltage gain is unity (i.e. 1 mV change on the gate is 1 mV change on the drain) and, you'd be right but importantly, you have JFET buffered the very weak and susceptible signal produced by the electret capsule. Of course, if you used a 6k8 drain resistor then voltage gain is 6.8. And, if you pick a JFET with a larger \$I_{DSS}\$ then you will also get more gain.
- > _If so, how would that work without a source resistor?_
- Quite well actually. If you look at the [2SK1109](https://www.renesas.com/en/document/dst/2sk1109-data-sheet) you'll see that it has this characteristic: -
- 
- I've highlighted the zero voltage bias point with a red rectangle. This is the situation you get when there is no source resistor. The drain current is about 60 to 75 μA over a range of drain voltages from 1 volt to 10 volts and, of course, if you have a signal on your gate, it will "modulate" the drain current up and down and this will be seen as a voltage waveform across the external drain pull-up resistor.
- This JFET is particularly suited to electret capsules because it only consumes tens to hundreds of microamps when quiescent. That as a specification is called \$I_{DSS}\$ and you want it to be generally sub 1 mA or you are just wasting power (especially important for battery applications).
- _What circuit voltage gain will you get with a 1 kΩ drain resistor?_
- The data sheet says that the forward transconductance is 1000 μS <-- that 1000 micro-siemens in case you thought it said micro-seconds. That is equivalent to 1 μA per millivolt meaning if you move the gate up and down a mV then the drain current is moved up and down by 1 μA. Into a 1 kΩ drain resistor that's a signal level of +/-1 mV.
- You might say at this point that the voltage gain is unity (i.e. 1 mV change on the gate is 1 mV change on the drain) and, you'd be right but importantly, you have buffered the very weak and susceptible signal produced by the electret capsule with the JFET. Of course, if you used a 6k8 drain resistor then the voltage gain is 6.8 and, if you pick a JFET with a larger \$I_{DSS}\$ then you will also get more gain.
#4: Post edited
by
Andy aka
·
2024-10-25T15:44:38Z (7 days ago)
- > _If so, how would that work without a source resistor?_
- Quite well actually. If you look at the [2SK1109](https://www.renesas.com/en/document/dst/2sk1109-data-sheet) you'll see that it has this characteristic: -
- 
- I've highlighted the zero voltage bias point with a red rectangle. This is the situation you get when there is no source resistor. The drain current is about 60 to 75 μA over a range of drain voltages from 1 volt to 10 volts and, of course, if you have a signal on your gate, it will "modulate" the drain current up and down and this will be seen as a voltage waveform across the external drain pull-up resistor.
This JFET is particularly suited to electret capsules because it only consumes tens to hundreds of microamps when quiescent. That as a specification is called \$I_{DSS}\$ and you want it to be generally sub 1 mA or you are just wasting power (especially important for battery applications).
- > _If so, how would that work without a source resistor?_
- Quite well actually. If you look at the [2SK1109](https://www.renesas.com/en/document/dst/2sk1109-data-sheet) you'll see that it has this characteristic: -
- 
- I've highlighted the zero voltage bias point with a red rectangle. This is the situation you get when there is no source resistor. The drain current is about 60 to 75 μA over a range of drain voltages from 1 volt to 10 volts and, of course, if you have a signal on your gate, it will "modulate" the drain current up and down and this will be seen as a voltage waveform across the external drain pull-up resistor.
- This JFET is particularly suited to electret capsules because it only consumes tens to hundreds of microamps when quiescent. That as a specification is called \$I_{DSS}\$ and you want it to be generally sub 1 mA or you are just wasting power (especially important for battery applications).
- _What circuit voltage gain will you get with a 1 kΩ drain resistor?_
- The data sheet says that the forward transconductance is 1000 μS <-- that 1000 micro-siemens in case you thought it said micro-seconds. That is equivalent to 1 μA per millivolt meaning if you move the gate up and down a mV then the drain current is moved up and down by 1 μA. Into a 1 kΩ drain resistor that's a signal level of +/-1 mV.
- You might say at this point that the voltage gain is unity (i.e. 1 mV change on the gate is 1 mV change on the drain) and, you'd be right but importantly, you have JFET buffered the very weak and susceptible signal produced by the electret capsule. Of course, if you used a 6k8 drain resistor then voltage gain is 6.8. And, if you pick a JFET with a larger \$I_{DSS}\$ then you will also get more gain.
#3: Post edited
by
Andy aka
·
2024-10-25T15:31:45Z (7 days ago)
- > _If so, how would that work without a source resistor?_
- Quite well actually. If you look at the [2SK1109](https://www.renesas.com/en/document/dst/2sk1109-data-sheet) you'll see that it has this characteristic: -
- 
I've highlighted the zero voltage bias point with a red rectangle. This is the situation you get when there is no source resistor. The drain current is about 60 to 75 μA across drain voltages from 1 volt to 10 volts and, of course, if you have a signal on your gate, it will "modulate" the drain current up and down and this will be seen as a voltage waveform across the external drain pull-up resistor.- This JFET is particularly suited to electret capsules because it only consumes tens to hundreds of microamps when quiescent. That as a specification is called \$I_{DSS}\$ and you want it to be generally sub 1 mA or you are just wasting power (especially important for battery applications).
- > _If so, how would that work without a source resistor?_
- Quite well actually. If you look at the [2SK1109](https://www.renesas.com/en/document/dst/2sk1109-data-sheet) you'll see that it has this characteristic: -
- 
- I've highlighted the zero voltage bias point with a red rectangle. This is the situation you get when there is no source resistor. The drain current is about 60 to 75 μA over a range of drain voltages from 1 volt to 10 volts and, of course, if you have a signal on your gate, it will "modulate" the drain current up and down and this will be seen as a voltage waveform across the external drain pull-up resistor.
- This JFET is particularly suited to electret capsules because it only consumes tens to hundreds of microamps when quiescent. That as a specification is called \$I_{DSS}\$ and you want it to be generally sub 1 mA or you are just wasting power (especially important for battery applications).
#2: Post edited
by
Andy aka
·
2024-10-25T15:30:35Z (7 days ago)
- > _If so, how would that work without a source resistor?_
Quite well actually. If you look at the [2SK1109](https://www.firstpr.com.au/rwi/mics/2009-09-b/2SK1109-datasheet.pdf) you'll see that it has this characteristic: -- 
- I've highlighted the zero voltage bias point with a red rectangle. This is the situation you get when there is no source resistor. The drain current is about 60 to 75 μA across drain voltages from 1 volt to 10 volts and, of course, if you have a signal on your gate, it will "modulate" the drain current up and down and this will be seen as a voltage waveform across the external drain pull-up resistor.
- This JFET is particularly suited to electret capsules because it only consumes tens to hundreds of microamps when quiescent. That as a specification is called \$I_{DSS}\$ and you want it to be generally sub 1 mA or you are just wasting power (especially important for battery applications).
- > _If so, how would that work without a source resistor?_
- Quite well actually. If you look at the [2SK1109](https://www.renesas.com/en/document/dst/2sk1109-data-sheet) you'll see that it has this characteristic: -
- 
- I've highlighted the zero voltage bias point with a red rectangle. This is the situation you get when there is no source resistor. The drain current is about 60 to 75 μA across drain voltages from 1 volt to 10 volts and, of course, if you have a signal on your gate, it will "modulate" the drain current up and down and this will be seen as a voltage waveform across the external drain pull-up resistor.
- This JFET is particularly suited to electret capsules because it only consumes tens to hundreds of microamps when quiescent. That as a specification is called \$I_{DSS}\$ and you want it to be generally sub 1 mA or you are just wasting power (especially important for battery applications).
#1: Initial revision
by
Andy aka
·
2024-10-25T15:28:50Z (7 days ago)
> _If so, how would that work without a source resistor?_
Quite well actually. If you look at the [2SK1109](https://www.firstpr.com.au/rwi/mics/2009-09-b/2SK1109-datasheet.pdf) you'll see that it has this characteristic: -
I've highlighted the zero voltage bias point with a red rectangle. This is the situation you get when there is no source resistor. The drain current is about 60 to 75 μA across drain voltages from 1 volt to 10 volts and, of course, if you have a signal on your gate, it will "modulate" the drain current up and down and this will be seen as a voltage waveform across the external drain pull-up resistor.
This JFET is particularly suited to electret capsules because it only consumes tens to hundreds of microamps when quiescent. That as a specification is called \$I_{DSS}\$ and you want it to be generally sub 1 mA or you are just wasting power (especially important for battery applications).