Post History

Your current FIFO acts as a standard FIFO. What you desire is a First Word Fall Through (FWFT) FIFO or a showahead FIFO. Changing the rd_data to be combinational logic instead of registered logic is the way to do this, the modification would look like this:

><pre>//read data from fifo
>
>always@(posedge clk)begin 
>   if(rd_en && !empty)begin 
>      //rd_data<=sync_fifo[rd_ptr]; // this would yield a value next cc
>       rd_ptr<=rd_ptr+1;
>   end
>end
>
>// remove 'reg' from rd_data port and make a continuous assignment
>assign rd_data = sync_fifo[rd_ptr];</pre>

![An image of GTKWave output from a simulation of the modified FIFO HDL that acts like a FWFT FIFO](https://electrical.codidact.com/uploads/sa2ssstda6wck0mral0pk9rrhk9f)

Changing the read enable (rd_en) net name to a read acknowledge (rd_ack) may be a more descriptive label in this case.

More information can be found at places like Eli Billauer's spin-off FPGA blog: https://www.01signal.com/using-ip/fpga-fifo/variants/