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If there are high slew rate signals or high-impedance circuits, layout matters. Otherwise, it usually doesn’t.

Slew Rate (SR) in the time domain translates to bandwidth in the frequency domain, so you can analyze it either way.

Technically, anything between 30 MHz and 300 MHz is considered high frequency (HF), where layout rules become important. Beyond that, they become critical.

**CPU Clock Signals:** 

While the CPU clock may be high-frequency, it’s only a small part of the circuit. However, high-speed signals should not pass under the crystal (Xtal) or run on long traces. If you use a ground plane under the crystal, consider its parasitic capacitance, as it affects load accuracy.

Switching Power Supply: Even if the switching frequency is low, fast current rise times can create ripple voltage. This can lead to harmonic interference, affecting AM/SW radios or regulatory compliance (FCC/CE).

-  Layout in this area is critical and should not be modified without understanding the consequences.

**High-Speed Signal Bandwidth:**

  Any exponential decay shorter than 12 µs corresponds to frequencies above 30 MHz.

 A 35 MHz clock is considered high-speed, and its harmonics extend up to the point where slew rate causes a null in the signal spectrum.

 Another approximation uses the 10%-90% rise time, where bandwidth is roughly BW = 0.50 / rise time.

**Impedances Control**

One should understand crosstalk, signal integrity, path distance, parasitic coupling, shielding, BER and SNR,  if you venture significantly above 10 k impedance. This isn't so much high speed as it is impedance control for resistance/reactance ratio for signal integrity.  You might not care about logic level overshoot when the rise time is faster than the path delay time but the impedance mismatch causes overshoot from 15 to 66 Ohm Vol/Io=Zo drivers to signal trace impedances more than a few inches. The ESD protection in CMOS may protect you but also beware your 10:1 probe ground length is another source of HF resonance ringing on fast edges if the ground lead is more than a few cm long. Normally you can ignore those with a 20 MHz filter on the DSO or use a proper high speed measurement technique with exposed probe tip and ring with a spring probe.
 
**Understanding Parasitics:**

Every conductor has parasitic capacitance due to insulation and parasitic inductance due to its geometry. 

These effects may be negligible at low frequencies but become significant in high-impedance or high-frequency circuits.

- Parasitic capacitance depends on area, gap, and dielectric constant. e.g 1" to 3" / pf for a trace over a ground plane, typ. There are free PCB design tool calculators for this.  
  - This affects high-impedance nodes like crystal oscillators or ADC inputs.  Generally, nothing is used below a crystal (Xtal) and load caps right next to it and uC pins. 

   -  Although it may/may not be surrounded by a ground guard ring or ground plane if EMI is critical and clock currents fanning out are a problem for EMI emissions. Just beware an isolated ground area can also become a weak patch antenna, if high slew rate currents flow through it, from zone to zone through parasitic ESL. 


- Parasitic inductance (ESL) is typically 0.8 nH/mm with ±50% variation.

**Best Practices:**

- Good schematics should note critical layout considerations, especially in power and RF designs.
- Many designs assume idealized ground symbols, but in reality, grounding should be carefully managed to minimize errors.

**Frequency Ranges:**
- ULF, VLF, LF, HF, VHF, UHF, etc., follow standard definitions.  
  High-speed circuits generally start at HF (30–300 MHz).