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Matching network considerations for STM32WB55CEU6

Hi,

I am designing a system using STM32WB55CEU6 and I want to use the RF functionality. Looking at evaluation board I see that there is a matching network for the output pin. The datasheet does not specify the output impedance, but an ST employee posted their empirical measurements:
![Image_alt_text](https://electrical.codidact.com/uploads/gaihulb3ux3b5vtgq8zh7p3hd3ly)

For the package I use the impedance is 42+j19. Using an online Smith chart tool it looks like I would only need a small 0.6pF capacitor:
![Image_alt_text](https://electrical.codidact.com/uploads/8e5oiwcp52ykm3sz5bek1bh0b13o)

However, the evaluation board uses a non-symmetric pi filter: ![Image_alt_text](https://electrical.codidact.com/uploads/3va5szkzmbpfcb7p73kzy11gz9kq)

It was my understanding that the advantage of a pi filter would be the symmetrical nature, where signal direction does not matter.

Therefore, it seems it would make sense to use symmetrical values as such: ![Image_alt_text](https://electrical.codidact.com/uploads/wjp37pnyhgr8mwsmtifuesj3xkqr)

Using the values provided by evaluation design:
![Image_alt_text](https://electrical.codidact.com/uploads/4gtp2y70q88zmssljrw7ycxj2enf)

This lands pretty far off. I see that in evaluation design it is mentioned component values will be updated after evaluation, so is it the case that these values are more or less arbitrary and tuned with a VNA during proto testing? What would be a reason to decide to use non-symmetrical pi filter for initial design? 

Regarding PCB design, most common thickness seems to be 1.6mm, however, with a 10% tolerance on the height could it be the case that the distance to return path changing from batch to batch could negatively impact performance of antenna, and therefore reducing overall thickness of the board prove beneficial to design?