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According to the datasheet, with the supply you are using the input voltage range is V<sub>-</sub> to V<sub>+</sub>-1.5.  With your 7 V supply, that comes out to 0 to 5.5 V.

You say the maximum differential input voltage is 2 V<sub>p-p</sub>.  With a bias of 2.5 V, that means that your input signals are limited to the 1.5 to 3.5 V range.  That leaves 1.5 V headroom at the low and and 2.0 V headroom at the high end.  The input voltage therefore seems to be well within spec.

The overall circuit seems fine as long as your signal source can tolerate the 8 k&Omega; load, and you are OK with the vaguely specified "600 kHz typical" bandwidth and associated poorly specified slew rates and settling times.

You say something about the 2.5 V reference being capacitively coupled, but nothing in your schematic nor the opamp description shows any capacitive coupling.  The schematic you show looks reasonable as far as it goes.  It would be better to see the schematic of the real circuit, not whatever was input to the simulator.  The gotchas are often in the implementation details.