Does preventing CMOS latchup with a diode in VCC path prevents protection diodes from working?
I want to use ADG726 multiplexer for an application where the multiplexer inputs could have potential on them before ADG726 is powered up. Seeing that ADG726 is a CMOS device, it seems it might be susceptible to latchup. One way to prevent it according to theory is to put a diode in series with the power rail, blocking current path when the device is powered off:
However, doesn't doing this also void input protection when the device is powered on? Looking at Absolute Maximum Ratings table it looks like the digital and analog inputs are clamped:
If the inputs exceed the VCC by the forward voltage of the input protection diode, the current cannot flow into the VCC rail due to the series diode. Is this indeed the case, and what better ways are there to protect against latchup while still maintaining input protection?
1 answer
Avoiding latchup with a diode in series with Vdd hadn't occurred to me before, and I've never heard of anyone doing that. I can see your point, but a few things make me nervous about this method:
- You would definitely need a cap on Vdd to keep the impedance low and the supply clean. That cap would be a leakage path to ground, if only for a short time as the input pin voltage was raised.
- Note that the parasitic SCR is self-sustaining once the PNP transistor is turned on. Current out of Vdd is therefore only needed for a short time to initially trigger the SCR. That doesn't work well with point 1.
- It only takes a little bit of leakage to get the SCR going, since there is positive feedback. Are you really sure that internal leakage is insufficient, especially at maximum temperature? What about capacitive coupling from nearby transients?
Overall, I wouldn't do this without it being specifically approved by the manufacturer. I'd want to see it mentioned as a possibility in the datasheet or an example in an app note or something.
Here is a snippet from one of my recent schematics where I addressed latchup in a different way:
AGPVOLT is an analog signal created by a resistor divider, shown elsewhere in the schematic. It is connected to an analog input pin of a microcontroller that gets powered up after AGPVOLT could be nearly the final Vdd of the micro. Q9 keeps AGPVOLT clamped low until INENAB is deliberately driven high. INENAB is a digital output from the same micro. The micro raises INENAB when it's ready to take analog readings, at which time of course it is fully powered up.
In this case there are multiple analog inputs that could be high before the micro is powered up. One combination like R23 and Q9 is connected to each such analog signal, although they are not shown in this snippet.
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