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You are using a P-channel MOSFET.  Pin 2 is the source, pin 3 the drain, and pin 1 the gate.

Note that the gate is only raised to ¾ of the input voltage when the 3.3V input is active. You didn't supply a link to the FET datasheet, so you need to check what kind of leakage is expected in that case.

If that doesn't explain what you see, then you probably have the drain and source of Q1 flipped.

Another problem is the way you draw schematics.  Obfuscating the circuit not only makes it more difficult for others to follow, but more likely you will make a mistake.  If you had drawn it more reasonably, you might have caught the mistake where the left end of R2 was connected in your previous question.  R1 and R2 are still a mess.  If you drew the schematic cleanly you might notice there is a better topology.

Asking others to look at a messy schematic is not respecting their time and effort.  If you don't care, why should I?