Post History
Old fashioned p-n junction devices suffered from a voltage drop (0.6V for Si, 0.2V for Ge, if I remember correctly). FETs and CMOS were the latest highlight back then, and highly prone to be destr...
#1: Initial revision
by
watchmaker
·
2025-10-26T18:02:13Z (11 months ago)
Avoid voltage loss and protect FETs from static energy
Old fashioned p-n junction devices suffered from a voltage drop (0.6V for Si, 0.2V for Ge, if I remember correctly).
FETs and CMOS were the latest highlight back then, and highly prone to be destructed from static electricity ("don't touch with your fingers").
That does not look like a problem nowadays.
How is that achieved?