Post History
immediate comments, going left to right in circuit: C61 ... can form undamped LC with input wiring, and thus overshoot to nearly twice Vin on plugin (or more likely some V a bit above Vbr at whi...
#20: Post edited
by
Pete W
·
2025-11-04T13:58:38Z (11 months ago)
- immediate comments, going left to right in circuit:
- * C61 ... can form undamped LC with input wiring, and thus overshoot to nearly twice Vin on plugin (or more likely some V a bit above Vbr at which TVS and the cap together eat the inrush). If placed right at the input, consider higher V rating?
- * D3 5.0SMDJ64A ... max Vbr =~ 79V (not to speak of Vcl). This is vs Q1 Vds_max=80V
- * D9 placement no good, will always conduct
- * Q1 in general ... how much current is used? Can you tolerate just using a large diode?
- * Q7 ... what's the rationale for the inner PMOS being different, and bigger, than the outer one?
- * U10/R59 ... are you sure 48V/100k = 480uA (nominal) will turn on the opto reliably enough?
- As to how to go about the latching functionality I'm reading from the description? TBH there are probably dedicated IC's for this, depending on the application. That aside, my thought would be to ensure that both the output node "+48V_SW" and the 3.3V node are thoroughly turned off.
- Below is an idea for the latching startup/shutdown functionality, without addressing the reverse voltage or transient protection. I am assuming an implicit requirement, to keep the PMOS off until the +48V_SW node has been brought down even lower than the voltage at which the MCU would turn off.
- Turn-on: Everything is off until the switch has been pressed. The switch creates a temporary turn-on path for the PMOS gate, which raises the +48V output node. That in turn energizes the 3.3V zener, and from that, the common-base NPN turns on thru the 3.3k resistor, keeping the PMOS on without needing the switch any more. I'd consider a small cap parallel to the 3.3V zener, just for peace of mind vs transients on the 48V node.
- Turn-off: Logic signals OFF_A or OFF_B activate the PNP-NPN shutdown-latch, bringing down the 3.3V that came from the zener - down to something in the neighborhood of 1V? At that voltage, the common-base will be off or weak enough that the PMOS should be off. It should be verified that the 3.3V rail is low enough in the latched-shutdown condition, that the MCU cannot turn on.
- 
Or using a flip-flop, with the logic family selected to keep its down to <1V on the 3.3V rail:- 
- immediate comments, going left to right in circuit:
- * C61 ... can form undamped LC with input wiring, and thus overshoot to nearly twice Vin on plugin (or more likely some V a bit above Vbr at which TVS and the cap together eat the inrush). If placed right at the input, consider higher V rating?
- * D3 5.0SMDJ64A ... max Vbr =~ 79V (not to speak of Vcl). This is vs Q1 Vds_max=80V
- * D9 placement no good, will always conduct
- * Q1 in general ... how much current is used? Can you tolerate just using a large diode?
- * Q7 ... what's the rationale for the inner PMOS being different, and bigger, than the outer one?
- * U10/R59 ... are you sure 48V/100k = 480uA (nominal) will turn on the opto reliably enough?
- As to how to go about the latching functionality I'm reading from the description? TBH there are probably dedicated IC's for this, depending on the application. That aside, my thought would be to ensure that both the output node "+48V_SW" and the 3.3V node are thoroughly turned off.
- Below is an idea for the latching startup/shutdown functionality, without addressing the reverse voltage or transient protection. I am assuming an implicit requirement, to keep the PMOS off until the +48V_SW node has been brought down even lower than the voltage at which the MCU would turn off.
- Turn-on: Everything is off until the switch has been pressed. The switch creates a temporary turn-on path for the PMOS gate, which raises the +48V output node. That in turn energizes the 3.3V zener, and from that, the common-base NPN turns on thru the 3.3k resistor, keeping the PMOS on without needing the switch any more. I'd consider a small cap parallel to the 3.3V zener, just for peace of mind vs transients on the 48V node.
- Turn-off: Logic signals OFF_A or OFF_B activate the PNP-NPN shutdown-latch, bringing down the 3.3V that came from the zener - down to something in the neighborhood of 1V? At that voltage, the common-base will be off or weak enough that the PMOS should be off. It should be verified that the 3.3V rail is low enough in the latched-shutdown condition, that the MCU cannot turn on.
- 
- Or using a flip-flop, with the logic family selected to keep its state down to <1V on the 3.3V rail:
- 
#19: Post edited
by
Pete W
·
2025-11-04T13:58:15Z (11 months ago)
- immediate comments, going left to right in circuit:
- * C61 ... can form undamped LC with input wiring, and thus overshoot to nearly twice Vin on plugin (or more likely some V a bit above Vbr at which TVS and the cap together eat the inrush). If placed right at the input, consider higher V rating?
- * D3 5.0SMDJ64A ... max Vbr =~ 79V (not to speak of Vcl). This is vs Q1 Vds_max=80V
- * D9 placement no good, will always conduct
- * Q1 in general ... how much current is used? Can you tolerate just using a large diode?
- * Q7 ... what's the rationale for the inner PMOS being different, and bigger, than the outer one?
- * U10/R59 ... are you sure 48V/100k = 480uA (nominal) will turn on the opto reliably enough?
- As to how to go about the latching functionality I'm reading from the description? TBH there are probably dedicated IC's for this, depending on the application. That aside, my thought would be to ensure that both the output node "+48V_SW" and the 3.3V node are thoroughly turned off.
- Below is an idea for the latching startup/shutdown functionality, without addressing the reverse voltage or transient protection. I am assuming an implicit requirement, to keep the PMOS off until the +48V_SW node has been brought down even lower than the voltage at which the MCU would turn off.
- Turn-on: Everything is off until the switch has been pressed. The switch creates a temporary turn-on path for the PMOS gate, which raises the +48V output node. That in turn energizes the 3.3V zener, and from that, the common-base NPN turns on thru the 3.3k resistor, keeping the PMOS on without needing the switch any more. I'd consider a small cap parallel to the 3.3V zener, just for peace of mind vs transients on the 48V node.
- Turn-off: Logic signals OFF_A or OFF_B activate the PNP-NPN shutdown-latch, bringing down the 3.3V that came from the zener - down to something in the neighborhood of 1V? At that voltage, the common-base will be off or weak enough that the PMOS should be off. It should be verified that the 3.3V rail is low enough in the latched-shutdown condition, that the MCU cannot turn on.
- immediate comments, going left to right in circuit:
- * C61 ... can form undamped LC with input wiring, and thus overshoot to nearly twice Vin on plugin (or more likely some V a bit above Vbr at which TVS and the cap together eat the inrush). If placed right at the input, consider higher V rating?
- * D3 5.0SMDJ64A ... max Vbr =~ 79V (not to speak of Vcl). This is vs Q1 Vds_max=80V
- * D9 placement no good, will always conduct
- * Q1 in general ... how much current is used? Can you tolerate just using a large diode?
- * Q7 ... what's the rationale for the inner PMOS being different, and bigger, than the outer one?
- * U10/R59 ... are you sure 48V/100k = 480uA (nominal) will turn on the opto reliably enough?
- As to how to go about the latching functionality I'm reading from the description? TBH there are probably dedicated IC's for this, depending on the application. That aside, my thought would be to ensure that both the output node "+48V_SW" and the 3.3V node are thoroughly turned off.
- Below is an idea for the latching startup/shutdown functionality, without addressing the reverse voltage or transient protection. I am assuming an implicit requirement, to keep the PMOS off until the +48V_SW node has been brought down even lower than the voltage at which the MCU would turn off.
- Turn-on: Everything is off until the switch has been pressed. The switch creates a temporary turn-on path for the PMOS gate, which raises the +48V output node. That in turn energizes the 3.3V zener, and from that, the common-base NPN turns on thru the 3.3k resistor, keeping the PMOS on without needing the switch any more. I'd consider a small cap parallel to the 3.3V zener, just for peace of mind vs transients on the 48V node.
- Turn-off: Logic signals OFF_A or OFF_B activate the PNP-NPN shutdown-latch, bringing down the 3.3V that came from the zener - down to something in the neighborhood of 1V? At that voltage, the common-base will be off or weak enough that the PMOS should be off. It should be verified that the 3.3V rail is low enough in the latched-shutdown condition, that the MCU cannot turn on.
- 
- Or using a flip-flop, with the logic family selected to keep its down to <1V on the 3.3V rail:
- 
#18: Post edited
by
Pete W
·
2025-11-04T05:25:59Z (11 months ago)
- immediate comments, going left to right in circuit:
- * C61 ... can form undamped LC with input wiring, and thus overshoot to nearly twice Vin on plugin (or more likely some V a bit above Vbr at which TVS and the cap together eat the inrush). If placed right at the input, consider higher V rating?
- * D3 5.0SMDJ64A ... max Vbr =~ 79V (not to speak of Vcl). This is vs Q1 Vds_max=80V
- * D9 placement no good, will always conduct
- * Q1 in general ... how much current is used? Can you tolerate just using a large diode?
* QF2/Q7 ... does the 3v3 rail depend on this circuit's output? Without 3v3 being available, QF2/Q7 will never turn on* U10 ... when opto is on, it will defeat ability of U4/U9/QF2 to turn Q7 off- * Q7 ... what's the rationale for the inner PMOS being different, and bigger, than the outer one?
* U10/R59 ... are you sure 48V/100k = 480uA (nominal) will turn it on reliably enough?- As to how to go about the latching functionality I'm reading from the description? TBH there are probably dedicated IC's for this, depending on the application. That aside, my thought would be to ensure that both the output node "+48V_SW" and the 3.3V node are thoroughly turned off.
- Below is an idea for the latching startup/shutdown functionality, without addressing the reverse voltage or transient protection. I am assuming an implicit requirement, to keep the PMOS off until the +48V_SW node has been brought down even lower than the voltage at which the MCU would turn off.
- Turn-on: Everything is off until the switch has been pressed. The switch creates a temporary turn-on path for the PMOS gate, which raises the +48V output node. That in turn energizes the 3.3V zener, and from that, the common-base NPN turns on thru the 3.3k resistor, keeping the PMOS on without needing the switch any more. I'd consider a small cap parallel to the 3.3V zener, just for peace of mind vs transients on the 48V node.
- Turn-off: Logic signals OFF_A or OFF_B activate the PNP-NPN shutdown-latch, bringing down the 3.3V that came from the zener - down to something in the neighborhood of 1V? At that voltage, the common-base will be off or weak enough that the PMOS should be off. It should be verified that the 3.3V rail is low enough in the latched-shutdown condition, that the MCU cannot turn on.
- 
- immediate comments, going left to right in circuit:
- * C61 ... can form undamped LC with input wiring, and thus overshoot to nearly twice Vin on plugin (or more likely some V a bit above Vbr at which TVS and the cap together eat the inrush). If placed right at the input, consider higher V rating?
- * D3 5.0SMDJ64A ... max Vbr =~ 79V (not to speak of Vcl). This is vs Q1 Vds_max=80V
- * D9 placement no good, will always conduct
- * Q1 in general ... how much current is used? Can you tolerate just using a large diode?
- * Q7 ... what's the rationale for the inner PMOS being different, and bigger, than the outer one?
- * U10/R59 ... are you sure 48V/100k = 480uA (nominal) will turn on the opto reliably enough?
- As to how to go about the latching functionality I'm reading from the description? TBH there are probably dedicated IC's for this, depending on the application. That aside, my thought would be to ensure that both the output node "+48V_SW" and the 3.3V node are thoroughly turned off.
- Below is an idea for the latching startup/shutdown functionality, without addressing the reverse voltage or transient protection. I am assuming an implicit requirement, to keep the PMOS off until the +48V_SW node has been brought down even lower than the voltage at which the MCU would turn off.
- Turn-on: Everything is off until the switch has been pressed. The switch creates a temporary turn-on path for the PMOS gate, which raises the +48V output node. That in turn energizes the 3.3V zener, and from that, the common-base NPN turns on thru the 3.3k resistor, keeping the PMOS on without needing the switch any more. I'd consider a small cap parallel to the 3.3V zener, just for peace of mind vs transients on the 48V node.
- Turn-off: Logic signals OFF_A or OFF_B activate the PNP-NPN shutdown-latch, bringing down the 3.3V that came from the zener - down to something in the neighborhood of 1V? At that voltage, the common-base will be off or weak enough that the PMOS should be off. It should be verified that the 3.3V rail is low enough in the latched-shutdown condition, that the MCU cannot turn on.
- 
#17: Post edited
by
Pete W
·
2025-11-04T05:19:08Z (11 months ago)
- immediate comments, going left to right in circuit:
- * C61 ... can form undamped LC with input wiring, and thus overshoot to nearly twice Vin on plugin (or more likely some V a bit above Vbr at which TVS and the cap together eat the inrush). If placed right at the input, consider higher V rating?
- * D3 5.0SMDJ64A ... max Vbr =~ 79V (not to speak of Vcl). This is vs Q1 Vds_max=80V
- * D9 placement no good, will always conduct
- * Q1 in general ... how much current is used? Can you tolerate just using a large diode?
- * QF2/Q7 ... does the 3v3 rail depend on this circuit's output? Without 3v3 being available, QF2/Q7 will never turn on
- * U10 ... when opto is on, it will defeat ability of U4/U9/QF2 to turn Q7 off
- * Q7 ... what's the rationale for the inner PMOS being different, and bigger, than the outer one?
- * U10/R59 ... are you sure 48V/100k = 480uA (nominal) will turn it on reliably enough?
- As to how to go about the latching functionality I'm reading from the description? TBH there are probably dedicated IC's for this, depending on the application. That aside, my thought would be to ensure that both the output node "+48V_SW" and the 3.3V node are thoroughly turned off.
- Below is an idea for the latching startup/shutdown functionality, without addressing the reverse voltage or transient protection. I am assuming an implicit requirement, to keep the PMOS off until the +48V_SW node has been brought down even lower than the voltage at which the MCU would turn off.
- Turn-on: Everything is off until the switch has been pressed. The switch creates a temporary turn-on path for the PMOS gate, which raises the +48V output node. That in turn energizes the 3.3V zener, and from that, the common-base NPN turns on thru the 3.3k resistor, keeping the PMOS on without needing the switch any more. I'd consider a small cap parallel to the 3.3V zener, just for peace of mind vs transients on the 48V node.
Turn-off: Logic signals OFF_A or OFF_B activate the PNP-NPN shutdown-latch, bringing down the 3.3V that came from the zener - down to something in the neighborhood of 1V? At that voltage, the common-base will be off or weak enough that the PMOS should be off. It should be verified that the 3.3V rail is low enough in the shutdown condition, that the MCU cannot turn on.- 
- immediate comments, going left to right in circuit:
- * C61 ... can form undamped LC with input wiring, and thus overshoot to nearly twice Vin on plugin (or more likely some V a bit above Vbr at which TVS and the cap together eat the inrush). If placed right at the input, consider higher V rating?
- * D3 5.0SMDJ64A ... max Vbr =~ 79V (not to speak of Vcl). This is vs Q1 Vds_max=80V
- * D9 placement no good, will always conduct
- * Q1 in general ... how much current is used? Can you tolerate just using a large diode?
- * QF2/Q7 ... does the 3v3 rail depend on this circuit's output? Without 3v3 being available, QF2/Q7 will never turn on
- * U10 ... when opto is on, it will defeat ability of U4/U9/QF2 to turn Q7 off
- * Q7 ... what's the rationale for the inner PMOS being different, and bigger, than the outer one?
- * U10/R59 ... are you sure 48V/100k = 480uA (nominal) will turn it on reliably enough?
- As to how to go about the latching functionality I'm reading from the description? TBH there are probably dedicated IC's for this, depending on the application. That aside, my thought would be to ensure that both the output node "+48V_SW" and the 3.3V node are thoroughly turned off.
- Below is an idea for the latching startup/shutdown functionality, without addressing the reverse voltage or transient protection. I am assuming an implicit requirement, to keep the PMOS off until the +48V_SW node has been brought down even lower than the voltage at which the MCU would turn off.
- Turn-on: Everything is off until the switch has been pressed. The switch creates a temporary turn-on path for the PMOS gate, which raises the +48V output node. That in turn energizes the 3.3V zener, and from that, the common-base NPN turns on thru the 3.3k resistor, keeping the PMOS on without needing the switch any more. I'd consider a small cap parallel to the 3.3V zener, just for peace of mind vs transients on the 48V node.
- Turn-off: Logic signals OFF_A or OFF_B activate the PNP-NPN shutdown-latch, bringing down the 3.3V that came from the zener - down to something in the neighborhood of 1V? At that voltage, the common-base will be off or weak enough that the PMOS should be off. It should be verified that the 3.3V rail is low enough in the latched-shutdown condition, that the MCU cannot turn on.
- 
#16: Post edited
by
Pete W
·
2025-11-04T05:18:48Z (11 months ago)
- immediate comments, going left to right in circuit:
- * C61 ... can form undamped LC with input wiring, and thus overshoot to nearly twice Vin on plugin (or more likely some V a bit above Vbr at which TVS and the cap together eat the inrush). If placed right at the input, consider higher V rating?
- * D3 5.0SMDJ64A ... max Vbr =~ 79V (not to speak of Vcl). This is vs Q1 Vds_max=80V
- * D9 placement no good, will always conduct
- * Q1 in general ... how much current is used? Can you tolerate just using a large diode?
- * QF2/Q7 ... does the 3v3 rail depend on this circuit's output? Without 3v3 being available, QF2/Q7 will never turn on
- * U10 ... when opto is on, it will defeat ability of U4/U9/QF2 to turn Q7 off
- * Q7 ... what's the rationale for the inner PMOS being different, and bigger, than the outer one?
- * U10/R59 ... are you sure 48V/100k = 480uA (nominal) will turn it on reliably enough?
- As to how to go about the latching functionality I'm reading from the description? TBH there are probably dedicated IC's for this, depending on the application. That aside, my thought would be to ensure that both the output node "+48V_SW" and the 3.3V node are thoroughly turned off.
- Below is an idea for the latching startup/shutdown functionality, without addressing the reverse voltage or transient protection. I am assuming an implicit requirement, to keep the PMOS off until the +48V_SW node has been brought down even lower than the voltage at which the MCU would turn off.
- Turn-on: Everything is off until the switch has been pressed. The switch creates a temporary turn-on path for the PMOS gate, which raises the +48V output node. That in turn energizes the 3.3V zener, and from that, the common-base NPN turns on thru the 3.3k resistor, keeping the PMOS on without needing the switch any more. I'd consider a small cap parallel to the 3.3V zener, just for peace of mind vs transients on the 48V node.
Turn-off: Logic signals OFF_A or OFF_B activate the PNP-NPN shutdown-latch, bringing down the 3.3V that came from the zener - down to something in the neighborhood of 1V? At that voltage, the common-base will be off or weak enough that the PMOS should be off. It should also be verified that the 3.3V rail is low enough in the shutdown condition, that the MCU cannot turn on.- 
- immediate comments, going left to right in circuit:
- * C61 ... can form undamped LC with input wiring, and thus overshoot to nearly twice Vin on plugin (or more likely some V a bit above Vbr at which TVS and the cap together eat the inrush). If placed right at the input, consider higher V rating?
- * D3 5.0SMDJ64A ... max Vbr =~ 79V (not to speak of Vcl). This is vs Q1 Vds_max=80V
- * D9 placement no good, will always conduct
- * Q1 in general ... how much current is used? Can you tolerate just using a large diode?
- * QF2/Q7 ... does the 3v3 rail depend on this circuit's output? Without 3v3 being available, QF2/Q7 will never turn on
- * U10 ... when opto is on, it will defeat ability of U4/U9/QF2 to turn Q7 off
- * Q7 ... what's the rationale for the inner PMOS being different, and bigger, than the outer one?
- * U10/R59 ... are you sure 48V/100k = 480uA (nominal) will turn it on reliably enough?
- As to how to go about the latching functionality I'm reading from the description? TBH there are probably dedicated IC's for this, depending on the application. That aside, my thought would be to ensure that both the output node "+48V_SW" and the 3.3V node are thoroughly turned off.
- Below is an idea for the latching startup/shutdown functionality, without addressing the reverse voltage or transient protection. I am assuming an implicit requirement, to keep the PMOS off until the +48V_SW node has been brought down even lower than the voltage at which the MCU would turn off.
- Turn-on: Everything is off until the switch has been pressed. The switch creates a temporary turn-on path for the PMOS gate, which raises the +48V output node. That in turn energizes the 3.3V zener, and from that, the common-base NPN turns on thru the 3.3k resistor, keeping the PMOS on without needing the switch any more. I'd consider a small cap parallel to the 3.3V zener, just for peace of mind vs transients on the 48V node.
- Turn-off: Logic signals OFF_A or OFF_B activate the PNP-NPN shutdown-latch, bringing down the 3.3V that came from the zener - down to something in the neighborhood of 1V? At that voltage, the common-base will be off or weak enough that the PMOS should be off. It should be verified that the 3.3V rail is low enough in the shutdown condition, that the MCU cannot turn on.
- 
#15: Post edited
by
Pete W
·
2025-11-04T05:17:26Z (11 months ago)
- immediate comments, going left to right in circuit:
- * C61 ... can form undamped LC with input wiring, and thus overshoot to nearly twice Vin on plugin (or more likely some V a bit above Vbr at which TVS and the cap together eat the inrush). If placed right at the input, consider higher V rating?
- * D3 5.0SMDJ64A ... max Vbr =~ 79V (not to speak of Vcl). This is vs Q1 Vds_max=80V
- * D9 placement no good, will always conduct
- * Q1 in general ... how much current is used? Can you tolerate just using a large diode?
- * QF2/Q7 ... does the 3v3 rail depend on this circuit's output? Without 3v3 being available, QF2/Q7 will never turn on
- * U10 ... when opto is on, it will defeat ability of U4/U9/QF2 to turn Q7 off
- * Q7 ... what's the rationale for the inner PMOS being different, and bigger, than the outer one?
- * U10/R59 ... are you sure 48V/100k = 480uA (nominal) will turn it on reliably enough?
- As to how to go about the latching functionality I'm reading from the description? TBH there are probably dedicated IC's for this, depending on the application. That aside, my thought would be to ensure that both the output node "+48V_SW" and the 3.3V node are thoroughly turned off.
- Below is an idea for the latching startup/shutdown functionality, without addressing the reverse voltage or transient protection. I am assuming an implicit requirement, to keep the PMOS off until the +48V_SW node has been brought down even lower than the voltage at which the MCU would turn off.
- Turn-on: Everything is off until the switch has been pressed. The switch creates a temporary turn-on path for the PMOS gate, which raises the +48V output node. That in turn energizes the 3.3V zener, and from that, the common-base NPN turns on thru the 3.3k resistor, keeping the PMOS on without needing the switch any more. I'd consider a small cap parallel to the 3.3V zener, just for peace of mind vs transients on the 48V node.
Turn-off: Logic signals OFF_A or OFF_B activate the PNP-NPN shutdown-latch, bringing down the 3.3V that came from the zener - down to something in the neighborhood of 1V. At that voltage, the common-base will be off or weak enough that the PMOS should be off (verify this!).It should also be verified that the 3.3V rail is low enough in the shutdown condition, that the MCU cannot turn on.- 
- immediate comments, going left to right in circuit:
- * C61 ... can form undamped LC with input wiring, and thus overshoot to nearly twice Vin on plugin (or more likely some V a bit above Vbr at which TVS and the cap together eat the inrush). If placed right at the input, consider higher V rating?
- * D3 5.0SMDJ64A ... max Vbr =~ 79V (not to speak of Vcl). This is vs Q1 Vds_max=80V
- * D9 placement no good, will always conduct
- * Q1 in general ... how much current is used? Can you tolerate just using a large diode?
- * QF2/Q7 ... does the 3v3 rail depend on this circuit's output? Without 3v3 being available, QF2/Q7 will never turn on
- * U10 ... when opto is on, it will defeat ability of U4/U9/QF2 to turn Q7 off
- * Q7 ... what's the rationale for the inner PMOS being different, and bigger, than the outer one?
- * U10/R59 ... are you sure 48V/100k = 480uA (nominal) will turn it on reliably enough?
- As to how to go about the latching functionality I'm reading from the description? TBH there are probably dedicated IC's for this, depending on the application. That aside, my thought would be to ensure that both the output node "+48V_SW" and the 3.3V node are thoroughly turned off.
- Below is an idea for the latching startup/shutdown functionality, without addressing the reverse voltage or transient protection. I am assuming an implicit requirement, to keep the PMOS off until the +48V_SW node has been brought down even lower than the voltage at which the MCU would turn off.
- Turn-on: Everything is off until the switch has been pressed. The switch creates a temporary turn-on path for the PMOS gate, which raises the +48V output node. That in turn energizes the 3.3V zener, and from that, the common-base NPN turns on thru the 3.3k resistor, keeping the PMOS on without needing the switch any more. I'd consider a small cap parallel to the 3.3V zener, just for peace of mind vs transients on the 48V node.
- Turn-off: Logic signals OFF_A or OFF_B activate the PNP-NPN shutdown-latch, bringing down the 3.3V that came from the zener - down to something in the neighborhood of 1V? At that voltage, the common-base will be off or weak enough that the PMOS should be off. It should also be verified that the 3.3V rail is low enough in the shutdown condition, that the MCU cannot turn on.
- 
#14: Post edited
by
Pete W
·
2025-11-04T05:13:42Z (11 months ago)
- immediate comments, going left to right in circuit:
- * C61 ... can form undamped LC with input wiring, and thus overshoot to nearly twice Vin on plugin (or more likely some V a bit above Vbr at which TVS and the cap together eat the inrush). If placed right at the input, consider higher V rating?
- * D3 5.0SMDJ64A ... max Vbr =~ 79V (not to speak of Vcl). This is vs Q1 Vds_max=80V
- * D9 placement no good, will always conduct
- * Q1 in general ... how much current is used? Can you tolerate just using a large diode?
- * QF2/Q7 ... does the 3v3 rail depend on this circuit's output? Without 3v3 being available, QF2/Q7 will never turn on
- * U10 ... when opto is on, it will defeat ability of U4/U9/QF2 to turn Q7 off
- * Q7 ... what's the rationale for the inner PMOS being different, and bigger, than the outer one?
- * U10/R59 ... are you sure 48V/100k = 480uA (nominal) will turn it on reliably enough?
- As to how to go about the latching functionality I'm reading from the description? TBH there are probably dedicated IC's for this, depending on the application. That aside, my thought would be to ensure that both the output node "+48V_SW" and the 3.3V node are thoroughly turned off.
- Below is an idea for the latching startup/shutdown functionality, without addressing the reverse voltage or transient protection. I am assuming an implicit requirement, to keep the PMOS off until the +48V_SW node has been brought down even lower than the voltage at which the MCU would turn off.
- Turn-on: Everything is off until the switch has been pressed. The switch creates a temporary turn-on path for the PMOS gate, which raises the +48V output node. That in turn energizes the 3.3V zener, and from that, the common-base NPN turns on thru the 3.3k resistor, keeping the PMOS on without needing the switch any more. I'd consider a small cap parallel to the 3.3V zener, just for peace of mind vs transients on the 48V node.
- Turn-off: Logic signals OFF_A or OFF_B activate the PNP-NPN shutdown-latch, bringing down the 3.3V that came from the zener - down to something in the neighborhood of 1V. At that voltage, the common-base will be off or weak enough that the PMOS should be off (verify this!).
- 
- immediate comments, going left to right in circuit:
- * C61 ... can form undamped LC with input wiring, and thus overshoot to nearly twice Vin on plugin (or more likely some V a bit above Vbr at which TVS and the cap together eat the inrush). If placed right at the input, consider higher V rating?
- * D3 5.0SMDJ64A ... max Vbr =~ 79V (not to speak of Vcl). This is vs Q1 Vds_max=80V
- * D9 placement no good, will always conduct
- * Q1 in general ... how much current is used? Can you tolerate just using a large diode?
- * QF2/Q7 ... does the 3v3 rail depend on this circuit's output? Without 3v3 being available, QF2/Q7 will never turn on
- * U10 ... when opto is on, it will defeat ability of U4/U9/QF2 to turn Q7 off
- * Q7 ... what's the rationale for the inner PMOS being different, and bigger, than the outer one?
- * U10/R59 ... are you sure 48V/100k = 480uA (nominal) will turn it on reliably enough?
- As to how to go about the latching functionality I'm reading from the description? TBH there are probably dedicated IC's for this, depending on the application. That aside, my thought would be to ensure that both the output node "+48V_SW" and the 3.3V node are thoroughly turned off.
- Below is an idea for the latching startup/shutdown functionality, without addressing the reverse voltage or transient protection. I am assuming an implicit requirement, to keep the PMOS off until the +48V_SW node has been brought down even lower than the voltage at which the MCU would turn off.
- Turn-on: Everything is off until the switch has been pressed. The switch creates a temporary turn-on path for the PMOS gate, which raises the +48V output node. That in turn energizes the 3.3V zener, and from that, the common-base NPN turns on thru the 3.3k resistor, keeping the PMOS on without needing the switch any more. I'd consider a small cap parallel to the 3.3V zener, just for peace of mind vs transients on the 48V node.
- Turn-off: Logic signals OFF_A or OFF_B activate the PNP-NPN shutdown-latch, bringing down the 3.3V that came from the zener - down to something in the neighborhood of 1V. At that voltage, the common-base will be off or weak enough that the PMOS should be off (verify this!).
- It should also be verified that the 3.3V rail is low enough in the shutdown condition, that the MCU cannot turn on.
- 
#13: Post edited
by
Pete W
·
2025-11-04T05:07:21Z (11 months ago)
- immediate comments, going left to right in circuit:
- * C61 ... can form undamped LC with input wiring, and thus overshoot to nearly twice Vin on plugin (or more likely some V a bit above Vbr at which TVS and the cap together eat the inrush). If placed right at the input, consider higher V rating?
- * D3 5.0SMDJ64A ... max Vbr =~ 79V (not to speak of Vcl). This is vs Q1 Vds_max=80V
- * D9 placement no good, will always conduct
- * Q1 in general ... how much current is used? Can you tolerate just using a large diode?
- * QF2/Q7 ... does the 3v3 rail depend on this circuit's output? Without 3v3 being available, QF2/Q7 will never turn on
- * U10 ... when opto is on, it will defeat ability of U4/U9/QF2 to turn Q7 off
- * Q7 ... what's the rationale for the inner PMOS being different, and bigger, than the outer one?
- * U10/R59 ... are you sure 48V/100k = 480uA (nominal) will turn it on reliably enough?
- As to how to go about the latching functionality I'm reading from the description? TBH there are probably dedicated IC's for this, depending on the application. That aside, my thought would be to ensure that both the output node "+48V_SW" and the 3.3V node are thoroughly turned off.
- Below is an idea for the latching startup/shutdown functionality, without addressing the reverse voltage or transient protection. I am assuming an implicit requirement, to keep the PMOS off until the +48V_SW node has been brought down even lower than the voltage at which the MCU would turn off.
- Turn-on: Everything is off until the switch has been pressed. The switch creates a temporary turn-on path for the PMOS gate, which raises the +48V output node. That in turn energizes the 3.3V zener, and from that, the common-base NPN turns on thru the 3.3k resistor, keeping the PMOS on without needing the switch any more. I'd consider a small cap parallel to the 3.3V zener, just for peace of mind vs transients on the 48V node.
Turn-off: Logic signals OFF_A or OFF_B activate the PNP-NPN shutdown-latch, bringing down the 3.3V that came from the zener - down to something in the neighborhood of 1V. At that voltage, the common-base will be off or weak enough that the PMOS should be off (verify this!). The shutdown-latch should remain active until the 48V output node's capacitance is nearly emptied out.- 
- immediate comments, going left to right in circuit:
- * C61 ... can form undamped LC with input wiring, and thus overshoot to nearly twice Vin on plugin (or more likely some V a bit above Vbr at which TVS and the cap together eat the inrush). If placed right at the input, consider higher V rating?
- * D3 5.0SMDJ64A ... max Vbr =~ 79V (not to speak of Vcl). This is vs Q1 Vds_max=80V
- * D9 placement no good, will always conduct
- * Q1 in general ... how much current is used? Can you tolerate just using a large diode?
- * QF2/Q7 ... does the 3v3 rail depend on this circuit's output? Without 3v3 being available, QF2/Q7 will never turn on
- * U10 ... when opto is on, it will defeat ability of U4/U9/QF2 to turn Q7 off
- * Q7 ... what's the rationale for the inner PMOS being different, and bigger, than the outer one?
- * U10/R59 ... are you sure 48V/100k = 480uA (nominal) will turn it on reliably enough?
- As to how to go about the latching functionality I'm reading from the description? TBH there are probably dedicated IC's for this, depending on the application. That aside, my thought would be to ensure that both the output node "+48V_SW" and the 3.3V node are thoroughly turned off.
- Below is an idea for the latching startup/shutdown functionality, without addressing the reverse voltage or transient protection. I am assuming an implicit requirement, to keep the PMOS off until the +48V_SW node has been brought down even lower than the voltage at which the MCU would turn off.
- Turn-on: Everything is off until the switch has been pressed. The switch creates a temporary turn-on path for the PMOS gate, which raises the +48V output node. That in turn energizes the 3.3V zener, and from that, the common-base NPN turns on thru the 3.3k resistor, keeping the PMOS on without needing the switch any more. I'd consider a small cap parallel to the 3.3V zener, just for peace of mind vs transients on the 48V node.
- Turn-off: Logic signals OFF_A or OFF_B activate the PNP-NPN shutdown-latch, bringing down the 3.3V that came from the zener - down to something in the neighborhood of 1V. At that voltage, the common-base will be off or weak enough that the PMOS should be off (verify this!).
- 
#12: Post edited
by
Pete W
·
2025-11-04T04:57:58Z (11 months ago)
- immediate comments, going left to right in circuit:
- * C61 ... can form undamped LC with input wiring, and thus overshoot to nearly twice Vin on plugin (or more likely some V a bit above Vbr at which TVS and the cap together eat the inrush). If placed right at the input, consider higher V rating?
- * D3 5.0SMDJ64A ... max Vbr =~ 79V (not to speak of Vcl). This is vs Q1 Vds_max=80V
- * D9 placement no good, will always conduct
- * Q1 in general ... how much current is used? Can you tolerate just using a large diode?
- * QF2/Q7 ... does the 3v3 rail depend on this circuit's output? Without 3v3 being available, QF2/Q7 will never turn on
- * U10 ... when opto is on, it will defeat ability of U4/U9/QF2 to turn Q7 off
- * Q7 ... what's the rationale for the inner PMOS being different, and bigger, than the outer one?
- * U10/R59 ... are you sure 48V/100k = 480uA (nominal) will turn it on reliably enough?
- As to how to go about the latching functionality I'm reading from the description? TBH there are probably dedicated IC's for this, depending on the application. That aside, my thought would be to ensure that both the output node "+48V_SW" and the 3.3V node are thoroughly turned off.
Below are two ideas for the latching startup/shutdown functionality, without addressing the reverse voltage or transient protection. The second one might be easier to start with for learning purposes.The first one has an implicit requirement, to keep the PMOS off until the +48V_SW node has been brought down even lower than the voltage at which the MCU would turn off.- Turn-on: Everything is off until the switch has been pressed. The switch creates a temporary turn-on path for the PMOS gate, which raises the +48V output node. That in turn energizes the 3.3V zener, and from that, the common-base NPN turns on thru the 3.3k resistor, keeping the PMOS on without needing the switch any more. I'd consider a small cap parallel to the 3.3V zener, just for peace of mind vs transients on the 48V node.
- Turn-off: Logic signals OFF_A or OFF_B activate the PNP-NPN shutdown-latch, bringing down the 3.3V that came from the zener - down to something in the neighborhood of 1V. At that voltage, the common-base will be off or weak enough that the PMOS should be off (verify this!). The shutdown-latch should remain active until the 48V output node's capacitance is nearly emptied out.
Simplified(?):The second circuit requires that once the MCU has turned off, everything is off and stays that way. The pull-ups on the OFF signals added because of a concern about the circuit restarting right after the MCU powers down at some UVLO level, and with the OFF_A/B tristated the common-base NPN could potentially still be sinking current from the PMOS gate, thwarting the shutdown. Also if the 3.3V rail is brought up some other way, it would on the 48V circuit.
- immediate comments, going left to right in circuit:
- * C61 ... can form undamped LC with input wiring, and thus overshoot to nearly twice Vin on plugin (or more likely some V a bit above Vbr at which TVS and the cap together eat the inrush). If placed right at the input, consider higher V rating?
- * D3 5.0SMDJ64A ... max Vbr =~ 79V (not to speak of Vcl). This is vs Q1 Vds_max=80V
- * D9 placement no good, will always conduct
- * Q1 in general ... how much current is used? Can you tolerate just using a large diode?
- * QF2/Q7 ... does the 3v3 rail depend on this circuit's output? Without 3v3 being available, QF2/Q7 will never turn on
- * U10 ... when opto is on, it will defeat ability of U4/U9/QF2 to turn Q7 off
- * Q7 ... what's the rationale for the inner PMOS being different, and bigger, than the outer one?
- * U10/R59 ... are you sure 48V/100k = 480uA (nominal) will turn it on reliably enough?
- As to how to go about the latching functionality I'm reading from the description? TBH there are probably dedicated IC's for this, depending on the application. That aside, my thought would be to ensure that both the output node "+48V_SW" and the 3.3V node are thoroughly turned off.
- Below is an idea for the latching startup/shutdown functionality, without addressing the reverse voltage or transient protection. I am assuming an implicit requirement, to keep the PMOS off until the +48V_SW node has been brought down even lower than the voltage at which the MCU would turn off.
- Turn-on: Everything is off until the switch has been pressed. The switch creates a temporary turn-on path for the PMOS gate, which raises the +48V output node. That in turn energizes the 3.3V zener, and from that, the common-base NPN turns on thru the 3.3k resistor, keeping the PMOS on without needing the switch any more. I'd consider a small cap parallel to the 3.3V zener, just for peace of mind vs transients on the 48V node.
- Turn-off: Logic signals OFF_A or OFF_B activate the PNP-NPN shutdown-latch, bringing down the 3.3V that came from the zener - down to something in the neighborhood of 1V. At that voltage, the common-base will be off or weak enough that the PMOS should be off (verify this!). The shutdown-latch should remain active until the 48V output node's capacitance is nearly emptied out.
- 
#11: Post edited
by
Pete W
·
2025-11-04T04:54:04Z (11 months ago)
- immediate comments, going left to right in circuit:
- * C61 ... can form undamped LC with input wiring, and thus overshoot to nearly twice Vin on plugin (or more likely some V a bit above Vbr at which TVS and the cap together eat the inrush). If placed right at the input, consider higher V rating?
- * D3 5.0SMDJ64A ... max Vbr =~ 79V (not to speak of Vcl). This is vs Q1 Vds_max=80V
- * D9 placement no good, will always conduct
- * Q1 in general ... how much current is used? Can you tolerate just using a large diode?
- * QF2/Q7 ... does the 3v3 rail depend on this circuit's output? Without 3v3 being available, QF2/Q7 will never turn on
- * U10 ... when opto is on, it will defeat ability of U4/U9/QF2 to turn Q7 off
- * Q7 ... what's the rationale for the inner PMOS being different, and bigger, than the outer one?
- * U10/R59 ... are you sure 48V/100k = 480uA (nominal) will turn it on reliably enough?
- As to how to go about the latching functionality I'm reading from the description? TBH there are probably dedicated IC's for this, depending on the application. That aside, my thought would be to ensure that both the output node "+48V_SW" and the 3.3V node are thoroughly turned off.
- Below are two ideas for the latching startup/shutdown functionality, without addressing the reverse voltage or transient protection. The second one might be easier to start with for learning purposes.
- The first one has an implicit requirement, to keep the PMOS off until the +48V_SW node has been brought down even lower than the voltage at which the MCU would turn off.
- Turn-on: Everything is off until the switch has been pressed. The switch creates a temporary turn-on path for the PMOS gate, which raises the +48V output node. That in turn energizes the 3.3V zener, and from that, the common-base NPN turns on thru the 3.3k resistor, keeping the PMOS on without needing the switch any more. I'd consider a small cap parallel to the 3.3V zener, just for peace of mind vs transients on the 48V node.
- Turn-off: Logic signals OFF_A or OFF_B activate the PNP-NPN shutdown-latch, bringing down the 3.3V that came from the zener - down to something in the neighborhood of 1V. At that voltage, the common-base will be off or weak enough that the PMOS should be off (verify this!). The shutdown-latch should remain active until the 48V output node's capacitance is nearly emptied out.
- Simplified(?):
- The second circuit requires that once the MCU has turned off, everything is off and stays that way. The pull-ups on the OFF signals added because of a concern about the circuit restarting right after the MCU powers down at some UVLO level, and with the OFF_A/B tristated the common-base NPN could potentially still be sinking current from the PMOS gate, thwarting the shutdown. Also if the 3.3V rail is brought up some other way, it would on the 48V circuit.
- 
- immediate comments, going left to right in circuit:
- * C61 ... can form undamped LC with input wiring, and thus overshoot to nearly twice Vin on plugin (or more likely some V a bit above Vbr at which TVS and the cap together eat the inrush). If placed right at the input, consider higher V rating?
- * D3 5.0SMDJ64A ... max Vbr =~ 79V (not to speak of Vcl). This is vs Q1 Vds_max=80V
- * D9 placement no good, will always conduct
- * Q1 in general ... how much current is used? Can you tolerate just using a large diode?
- * QF2/Q7 ... does the 3v3 rail depend on this circuit's output? Without 3v3 being available, QF2/Q7 will never turn on
- * U10 ... when opto is on, it will defeat ability of U4/U9/QF2 to turn Q7 off
- * Q7 ... what's the rationale for the inner PMOS being different, and bigger, than the outer one?
- * U10/R59 ... are you sure 48V/100k = 480uA (nominal) will turn it on reliably enough?
- As to how to go about the latching functionality I'm reading from the description? TBH there are probably dedicated IC's for this, depending on the application. That aside, my thought would be to ensure that both the output node "+48V_SW" and the 3.3V node are thoroughly turned off.
- Below are two ideas for the latching startup/shutdown functionality, without addressing the reverse voltage or transient protection. The second one might be easier to start with for learning purposes.
- The first one has an implicit requirement, to keep the PMOS off until the +48V_SW node has been brought down even lower than the voltage at which the MCU would turn off.
- Turn-on: Everything is off until the switch has been pressed. The switch creates a temporary turn-on path for the PMOS gate, which raises the +48V output node. That in turn energizes the 3.3V zener, and from that, the common-base NPN turns on thru the 3.3k resistor, keeping the PMOS on without needing the switch any more. I'd consider a small cap parallel to the 3.3V zener, just for peace of mind vs transients on the 48V node.
- Turn-off: Logic signals OFF_A or OFF_B activate the PNP-NPN shutdown-latch, bringing down the 3.3V that came from the zener - down to something in the neighborhood of 1V. At that voltage, the common-base will be off or weak enough that the PMOS should be off (verify this!). The shutdown-latch should remain active until the 48V output node's capacitance is nearly emptied out.
- 
- Simplified(?):
- The second circuit requires that once the MCU has turned off, everything is off and stays that way. The pull-ups on the OFF signals added because of a concern about the circuit restarting right after the MCU powers down at some UVLO level, and with the OFF_A/B tristated the common-base NPN could potentially still be sinking current from the PMOS gate, thwarting the shutdown. Also if the 3.3V rail is brought up some other way, it would on the 48V circuit.
- 
#10: Post edited
by
Pete W
·
2025-11-04T04:52:53Z (11 months ago)
- immediate comments, going left to right in circuit:
- * C61 ... can form undamped LC with input wiring, and thus overshoot to nearly twice Vin on plugin (or more likely some V a bit above Vbr at which TVS and the cap together eat the inrush). If placed right at the input, consider higher V rating?
- * D3 5.0SMDJ64A ... max Vbr =~ 79V (not to speak of Vcl). This is vs Q1 Vds_max=80V
- * D9 placement no good, will always conduct
- * Q1 in general ... how much current is used? Can you tolerate just using a large diode?
- * QF2/Q7 ... does the 3v3 rail depend on this circuit's output? Without 3v3 being available, QF2/Q7 will never turn on
- * U10 ... when opto is on, it will defeat ability of U4/U9/QF2 to turn Q7 off
- * Q7 ... what's the rationale for the inner PMOS being different, and bigger, than the outer one?
- * U10/R59 ... are you sure 48V/100k = 480uA (nominal) will turn it on reliably enough?
- As to how to go about the latching functionality I'm reading from the description? TBH there are probably dedicated IC's for this, depending on the application. That aside, my thought would be to ensure that both the output node "+48V_SW" and the 3.3V node are thoroughly turned off.
- Below are two ideas for the latching startup/shutdown functionality, without addressing the reverse voltage or transient protection. The second one might be easier to start with for learning purposes.
- The first one has an implicit requirement, to keep the PMOS off until the +48V_SW node has been brought down even lower than the voltage at which the MCU would turn off.
- Turn-on: Everything is off until the switch has been pressed. The switch creates a temporary turn-on path for the PMOS gate, which raises the +48V output node. That in turn energizes the 3.3V zener, and from that, the common-base NPN turns on thru the 3.3k resistor, keeping the PMOS on without needing the switch any more. I'd consider a small cap parallel to the 3.3V zener, just for peace of mind vs transients on the 48V node.
- Turn-off: Logic signals OFF_A or OFF_B activate the PNP-NPN shutdown-latch, bringing down the 3.3V that came from the zener - down to something in the neighborhood of 1V. At that voltage, the common-base will be off or weak enough that the PMOS should be off (verify this!). The shutdown-latch should remain active until the 48V output node's capacitance is nearly emptied out.
- 
- Simplified(?):
The second circuit requires that once the MCU has turned off, everything is off and stays that way. The pull-ups on the OFF signals added because of a concern about the circuit restarting right after the MCU powers down at some UVLO level, and with the OFF_A/B tristated the common-base NPN could potentially still be sinking current from the PMOS gate, thwarting the shutdown. Also if the 3.3V rail is brought up some other way, it would on the 48V circuit, which might be undesireable.- 
- immediate comments, going left to right in circuit:
- * C61 ... can form undamped LC with input wiring, and thus overshoot to nearly twice Vin on plugin (or more likely some V a bit above Vbr at which TVS and the cap together eat the inrush). If placed right at the input, consider higher V rating?
- * D3 5.0SMDJ64A ... max Vbr =~ 79V (not to speak of Vcl). This is vs Q1 Vds_max=80V
- * D9 placement no good, will always conduct
- * Q1 in general ... how much current is used? Can you tolerate just using a large diode?
- * QF2/Q7 ... does the 3v3 rail depend on this circuit's output? Without 3v3 being available, QF2/Q7 will never turn on
- * U10 ... when opto is on, it will defeat ability of U4/U9/QF2 to turn Q7 off
- * Q7 ... what's the rationale for the inner PMOS being different, and bigger, than the outer one?
- * U10/R59 ... are you sure 48V/100k = 480uA (nominal) will turn it on reliably enough?
- As to how to go about the latching functionality I'm reading from the description? TBH there are probably dedicated IC's for this, depending on the application. That aside, my thought would be to ensure that both the output node "+48V_SW" and the 3.3V node are thoroughly turned off.
- Below are two ideas for the latching startup/shutdown functionality, without addressing the reverse voltage or transient protection. The second one might be easier to start with for learning purposes.
- The first one has an implicit requirement, to keep the PMOS off until the +48V_SW node has been brought down even lower than the voltage at which the MCU would turn off.
- Turn-on: Everything is off until the switch has been pressed. The switch creates a temporary turn-on path for the PMOS gate, which raises the +48V output node. That in turn energizes the 3.3V zener, and from that, the common-base NPN turns on thru the 3.3k resistor, keeping the PMOS on without needing the switch any more. I'd consider a small cap parallel to the 3.3V zener, just for peace of mind vs transients on the 48V node.
- Turn-off: Logic signals OFF_A or OFF_B activate the PNP-NPN shutdown-latch, bringing down the 3.3V that came from the zener - down to something in the neighborhood of 1V. At that voltage, the common-base will be off or weak enough that the PMOS should be off (verify this!). The shutdown-latch should remain active until the 48V output node's capacitance is nearly emptied out.
- 
- Simplified(?):
- The second circuit requires that once the MCU has turned off, everything is off and stays that way. The pull-ups on the OFF signals added because of a concern about the circuit restarting right after the MCU powers down at some UVLO level, and with the OFF_A/B tristated the common-base NPN could potentially still be sinking current from the PMOS gate, thwarting the shutdown. Also if the 3.3V rail is brought up some other way, it would on the 48V circuit.
- 
#9: Post edited
by
Pete W
·
2025-11-04T04:52:31Z (11 months ago)
- immediate comments, going left to right in circuit:
- * C61 ... can form undamped LC with input wiring, and thus overshoot to nearly twice Vin on plugin (or more likely some V a bit above Vbr at which TVS and the cap together eat the inrush). If placed right at the input, consider higher V rating?
- * D3 5.0SMDJ64A ... max Vbr =~ 79V (not to speak of Vcl). This is vs Q1 Vds_max=80V
- * D9 placement no good, will always conduct
- * Q1 in general ... how much current is used? Can you tolerate just using a large diode?
- * QF2/Q7 ... does the 3v3 rail depend on this circuit's output? Without 3v3 being available, QF2/Q7 will never turn on
- * U10 ... when opto is on, it will defeat ability of U4/U9/QF2 to turn Q7 off
- * Q7 ... what's the rationale for the inner PMOS being different, and bigger, than the outer one?
- * U10/R59 ... are you sure 48V/100k = 480uA (nominal) will turn it on reliably enough?
- As to how to go about the latching functionality I'm reading from the description? TBH there are probably dedicated IC's for this, depending on the application. That aside, my thought would be to ensure that both the output node "+48V_SW" and the 3.3V node are thoroughly turned off.
- Below are two ideas for the latching startup/shutdown functionality, without addressing the reverse voltage or transient protection. The second one might be easier to start with for learning purposes.
- The first one has an implicit requirement, to keep the PMOS off until the +48V_SW node has been brought down even lower than the voltage at which the MCU would turn off.
- Turn-on: Everything is off until the switch has been pressed. The switch creates a temporary turn-on path for the PMOS gate, which raises the +48V output node. That in turn energizes the 3.3V zener, and from that, the common-base NPN turns on thru the 3.3k resistor, keeping the PMOS on without needing the switch any more. I'd consider a small cap parallel to the 3.3V zener, just for peace of mind vs transients on the 48V node.
- Turn-off: Logic signals OFF_A or OFF_B activate the PNP-NPN shutdown-latch, bringing down the 3.3V that came from the zener - down to something in the neighborhood of 1V. At that voltage, the common-base will be off or weak enough that the PMOS should be off (verify this!). The shutdown-latch should remain active until the 48V output node's capacitance is nearly emptied out.
- 
- Simplified(?):
The second circuit requires that once the MCU has turned off, everything is off and stays that way. The pull-ups on the OFF signals added because of a concern about the circuit restarting right after the MCU powers down at some UVLO level, and with the OFF_A/B tristated the common-base NPN could potentially still be sinking current from the PMOS gate, thwarting the shutdown. Also if the 3.3V rail is brought up some other way, it would on the main circuit, which might be undesireable.- 
- immediate comments, going left to right in circuit:
- * C61 ... can form undamped LC with input wiring, and thus overshoot to nearly twice Vin on plugin (or more likely some V a bit above Vbr at which TVS and the cap together eat the inrush). If placed right at the input, consider higher V rating?
- * D3 5.0SMDJ64A ... max Vbr =~ 79V (not to speak of Vcl). This is vs Q1 Vds_max=80V
- * D9 placement no good, will always conduct
- * Q1 in general ... how much current is used? Can you tolerate just using a large diode?
- * QF2/Q7 ... does the 3v3 rail depend on this circuit's output? Without 3v3 being available, QF2/Q7 will never turn on
- * U10 ... when opto is on, it will defeat ability of U4/U9/QF2 to turn Q7 off
- * Q7 ... what's the rationale for the inner PMOS being different, and bigger, than the outer one?
- * U10/R59 ... are you sure 48V/100k = 480uA (nominal) will turn it on reliably enough?
- As to how to go about the latching functionality I'm reading from the description? TBH there are probably dedicated IC's for this, depending on the application. That aside, my thought would be to ensure that both the output node "+48V_SW" and the 3.3V node are thoroughly turned off.
- Below are two ideas for the latching startup/shutdown functionality, without addressing the reverse voltage or transient protection. The second one might be easier to start with for learning purposes.
- The first one has an implicit requirement, to keep the PMOS off until the +48V_SW node has been brought down even lower than the voltage at which the MCU would turn off.
- Turn-on: Everything is off until the switch has been pressed. The switch creates a temporary turn-on path for the PMOS gate, which raises the +48V output node. That in turn energizes the 3.3V zener, and from that, the common-base NPN turns on thru the 3.3k resistor, keeping the PMOS on without needing the switch any more. I'd consider a small cap parallel to the 3.3V zener, just for peace of mind vs transients on the 48V node.
- Turn-off: Logic signals OFF_A or OFF_B activate the PNP-NPN shutdown-latch, bringing down the 3.3V that came from the zener - down to something in the neighborhood of 1V. At that voltage, the common-base will be off or weak enough that the PMOS should be off (verify this!). The shutdown-latch should remain active until the 48V output node's capacitance is nearly emptied out.
- 
- Simplified(?):
- The second circuit requires that once the MCU has turned off, everything is off and stays that way. The pull-ups on the OFF signals added because of a concern about the circuit restarting right after the MCU powers down at some UVLO level, and with the OFF_A/B tristated the common-base NPN could potentially still be sinking current from the PMOS gate, thwarting the shutdown. Also if the 3.3V rail is brought up some other way, it would on the 48V circuit, which might be undesireable.
- 
#8: Post edited
by
Pete W
·
2025-11-04T04:52:07Z (11 months ago)
- immediate comments, going left to right in circuit:
- * C61 ... can form undamped LC with input wiring, and thus overshoot to nearly twice Vin on plugin (or more likely some V a bit above Vbr at which TVS and the cap together eat the inrush). If placed right at the input, consider higher V rating?
- * D3 5.0SMDJ64A ... max Vbr =~ 79V (not to speak of Vcl). This is vs Q1 Vds_max=80V
- * D9 placement no good, will always conduct
- * Q1 in general ... how much current is used? Can you tolerate just using a large diode?
- * QF2/Q7 ... does the 3v3 rail depend on this circuit's output? Without 3v3 being available, QF2/Q7 will never turn on
- * U10 ... when opto is on, it will defeat ability of U4/U9/QF2 to turn Q7 off
- * Q7 ... what's the rationale for the inner PMOS being different, and bigger, than the outer one?
- * U10/R59 ... are you sure 48V/100k = 480uA (nominal) will turn it on reliably enough?
- As to how to go about the latching functionality I'm reading from the description? TBH there are probably dedicated IC's for this, depending on the application. That aside, my thought would be to ensure that both the output node "+48V_SW" and the 3.3V node are thoroughly turned off.
- Below are two ideas for the latching startup/shutdown functionality, without addressing the reverse voltage or transient protection. The second one might be easier to start with for learning purposes.
- The first one has an implicit requirement, to keep the PMOS off until the +48V_SW node has been brought down even lower than the voltage at which the MCU would turn off.
- Turn-on: Everything is off until the switch has been pressed. The switch creates a temporary turn-on path for the PMOS gate, which raises the +48V output node. That in turn energizes the 3.3V zener, and from that, the common-base NPN turns on thru the 3.3k resistor, keeping the PMOS on without needing the switch any more. I'd consider a small cap parallel to the 3.3V zener, just for peace of mind vs transients on the 48V node.
- Turn-off: Logic signals OFF_A or OFF_B activate the PNP-NPN shutdown-latch, bringing down the 3.3V that came from the zener - down to something in the neighborhood of 1V. At that voltage, the common-base will be off or weak enough that the PMOS should be off (verify this!). The shutdown-latch should remain active until the 48V output node's capacitance is nearly emptied out.
- 
- Simplified(?):
The second circuit requires that once the MCU has turned off, everything is off and stays that way. The pull-ups on the OFF signals added because of a concern about the circuit restarting right after the MCU powers down at some UVLO level, and with the OFF_A/B tristated the common-base NPN could potentially still be sinking current from the PMOS gate, thwarting the shutdown.- 
- immediate comments, going left to right in circuit:
- * C61 ... can form undamped LC with input wiring, and thus overshoot to nearly twice Vin on plugin (or more likely some V a bit above Vbr at which TVS and the cap together eat the inrush). If placed right at the input, consider higher V rating?
- * D3 5.0SMDJ64A ... max Vbr =~ 79V (not to speak of Vcl). This is vs Q1 Vds_max=80V
- * D9 placement no good, will always conduct
- * Q1 in general ... how much current is used? Can you tolerate just using a large diode?
- * QF2/Q7 ... does the 3v3 rail depend on this circuit's output? Without 3v3 being available, QF2/Q7 will never turn on
- * U10 ... when opto is on, it will defeat ability of U4/U9/QF2 to turn Q7 off
- * Q7 ... what's the rationale for the inner PMOS being different, and bigger, than the outer one?
- * U10/R59 ... are you sure 48V/100k = 480uA (nominal) will turn it on reliably enough?
- As to how to go about the latching functionality I'm reading from the description? TBH there are probably dedicated IC's for this, depending on the application. That aside, my thought would be to ensure that both the output node "+48V_SW" and the 3.3V node are thoroughly turned off.
- Below are two ideas for the latching startup/shutdown functionality, without addressing the reverse voltage or transient protection. The second one might be easier to start with for learning purposes.
- The first one has an implicit requirement, to keep the PMOS off until the +48V_SW node has been brought down even lower than the voltage at which the MCU would turn off.
- Turn-on: Everything is off until the switch has been pressed. The switch creates a temporary turn-on path for the PMOS gate, which raises the +48V output node. That in turn energizes the 3.3V zener, and from that, the common-base NPN turns on thru the 3.3k resistor, keeping the PMOS on without needing the switch any more. I'd consider a small cap parallel to the 3.3V zener, just for peace of mind vs transients on the 48V node.
- Turn-off: Logic signals OFF_A or OFF_B activate the PNP-NPN shutdown-latch, bringing down the 3.3V that came from the zener - down to something in the neighborhood of 1V. At that voltage, the common-base will be off or weak enough that the PMOS should be off (verify this!). The shutdown-latch should remain active until the 48V output node's capacitance is nearly emptied out.
- 
- Simplified(?):
- The second circuit requires that once the MCU has turned off, everything is off and stays that way. The pull-ups on the OFF signals added because of a concern about the circuit restarting right after the MCU powers down at some UVLO level, and with the OFF_A/B tristated the common-base NPN could potentially still be sinking current from the PMOS gate, thwarting the shutdown. Also if the 3.3V rail is brought up some other way, it would on the main circuit, which might be undesireable.
- 
#7: Post edited
by
Pete W
·
2025-11-04T04:50:07Z (11 months ago)
- immediate comments, going left to right in circuit:
- * C61 ... can form undamped LC with input wiring, and thus overshoot to nearly twice Vin on plugin (or more likely some V a bit above Vbr at which TVS and the cap together eat the inrush). If placed right at the input, consider higher V rating?
- * D3 5.0SMDJ64A ... max Vbr =~ 79V (not to speak of Vcl). This is vs Q1 Vds_max=80V
- * D9 placement no good, will always conduct
- * Q1 in general ... how much current is used? Can you tolerate just using a large diode?
- * QF2/Q7 ... does the 3v3 rail depend on this circuit's output? Without 3v3 being available, QF2/Q7 will never turn on
- * U10 ... when opto is on, it will defeat ability of U4/U9/QF2 to turn Q7 off
- * Q7 ... what's the rationale for the inner PMOS being different, and bigger, than the outer one?
- * U10/R59 ... are you sure 48V/100k = 480uA (nominal) will turn it on reliably enough?
- As to how to go about the latching functionality I'm reading from the description? TBH there are probably dedicated IC's for this, depending on the application. That aside, my thought would be to ensure that both the output node "+48V_SW" and the 3.3V node are thoroughly turned off.
- Below are two ideas for the latching startup/shutdown functionality, without addressing the reverse voltage or transient protection. The second one might be easier to start with for learning purposes.
- The first one has an implicit requirement, to keep the PMOS off until the +48V_SW node has been brought down even lower than the voltage at which the MCU would turn off.
- Turn-on: Everything is off until the switch has been pressed. The switch creates a temporary turn-on path for the PMOS gate, which raises the +48V output node. That in turn energizes the 3.3V zener, and from that, the common-base NPN turns on thru the 3.3k resistor, keeping the PMOS on without needing the switch any more. I'd consider a small cap parallel to the 3.3V zener, just for peace of mind vs transients on the 48V node.
- Turn-off: Logic signals OFF_A or OFF_B activate the PNP-NPN shutdown-latch, bringing down the 3.3V that came from the zener - down to something in the neighborhood of 1V. At that voltage, the common-base will be off or weak enough that the PMOS should be off (verify this!). The shutdown-latch should remain active until the 48V output node's capacitance is nearly emptied out.
- 
- Simplified(?):
The second circuit assumes that once the MCU has turned off, everything is off and stays that way. Not entirely confident that would be the case. For instance if the "3.3V" node were at something like 2V when the MCU turns off, the OFF_A/OFF_B signals would tristate, and the common-base NPN could turn back on (albeit weakly), potentially restarting everything depending on the MCU's actual UVLO voltage.
- immediate comments, going left to right in circuit:
- * C61 ... can form undamped LC with input wiring, and thus overshoot to nearly twice Vin on plugin (or more likely some V a bit above Vbr at which TVS and the cap together eat the inrush). If placed right at the input, consider higher V rating?
- * D3 5.0SMDJ64A ... max Vbr =~ 79V (not to speak of Vcl). This is vs Q1 Vds_max=80V
- * D9 placement no good, will always conduct
- * Q1 in general ... how much current is used? Can you tolerate just using a large diode?
- * QF2/Q7 ... does the 3v3 rail depend on this circuit's output? Without 3v3 being available, QF2/Q7 will never turn on
- * U10 ... when opto is on, it will defeat ability of U4/U9/QF2 to turn Q7 off
- * Q7 ... what's the rationale for the inner PMOS being different, and bigger, than the outer one?
- * U10/R59 ... are you sure 48V/100k = 480uA (nominal) will turn it on reliably enough?
- As to how to go about the latching functionality I'm reading from the description? TBH there are probably dedicated IC's for this, depending on the application. That aside, my thought would be to ensure that both the output node "+48V_SW" and the 3.3V node are thoroughly turned off.
- Below are two ideas for the latching startup/shutdown functionality, without addressing the reverse voltage or transient protection. The second one might be easier to start with for learning purposes.
- The first one has an implicit requirement, to keep the PMOS off until the +48V_SW node has been brought down even lower than the voltage at which the MCU would turn off.
- Turn-on: Everything is off until the switch has been pressed. The switch creates a temporary turn-on path for the PMOS gate, which raises the +48V output node. That in turn energizes the 3.3V zener, and from that, the common-base NPN turns on thru the 3.3k resistor, keeping the PMOS on without needing the switch any more. I'd consider a small cap parallel to the 3.3V zener, just for peace of mind vs transients on the 48V node.
- Turn-off: Logic signals OFF_A or OFF_B activate the PNP-NPN shutdown-latch, bringing down the 3.3V that came from the zener - down to something in the neighborhood of 1V. At that voltage, the common-base will be off or weak enough that the PMOS should be off (verify this!). The shutdown-latch should remain active until the 48V output node's capacitance is nearly emptied out.
- 
- Simplified(?):
- The second circuit requires that once the MCU has turned off, everything is off and stays that way. The pull-ups on the OFF signals added because of a concern about the circuit restarting right after the MCU powers down at some UVLO level, and with the OFF_A/B tristated the common-base NPN could potentially still be sinking current from the PMOS gate, thwarting the shutdown.
- 
#6: Post edited
by
Pete W
·
2025-11-04T04:43:04Z (11 months ago)
- immediate comments, going left to right in circuit:
- * C61 ... can form undamped LC with input wiring, and thus overshoot to nearly twice Vin on plugin (or more likely some V a bit above Vbr at which TVS and the cap together eat the inrush). If placed right at the input, consider higher V rating?
- * D3 5.0SMDJ64A ... max Vbr =~ 79V (not to speak of Vcl). This is vs Q1 Vds_max=80V
- * D9 placement no good, will always conduct
- * Q1 in general ... how much current is used? Can you tolerate just using a large diode?
- * QF2/Q7 ... does the 3v3 rail depend on this circuit's output? Without 3v3 being available, QF2/Q7 will never turn on
- * U10 ... when opto is on, it will defeat ability of U4/U9/QF2 to turn Q7 off
- * Q7 ... what's the rationale for the inner PMOS being different, and bigger, than the outer one?
- * U10/R59 ... are you sure 48V/100k = 480uA (nominal) will turn it on reliably enough?
* U10 doesn't seem to be doing much isolation anyway?- As to how to go about the latching functionality I'm reading from the description? TBH there are probably dedicated IC's for this, depending on the application. That aside, my thought would be to ensure that both the output node "+48V_SW" and the 3.3V node are thoroughly turned off.
- Below are two ideas for the latching startup/shutdown functionality, without addressing the reverse voltage or transient protection. The second one might be easier to start with for learning purposes.
- The first one has an implicit requirement, to keep the PMOS off until the +48V_SW node has been brought down even lower than the voltage at which the MCU would turn off.
- Turn-on: Everything is off until the switch has been pressed. The switch creates a temporary turn-on path for the PMOS gate, which raises the +48V output node. That in turn energizes the 3.3V zener, and from that, the common-base NPN turns on thru the 3.3k resistor, keeping the PMOS on without needing the switch any more. I'd consider a small cap parallel to the 3.3V zener, just for peace of mind vs transients on the 48V node.
- Turn-off: Logic signals OFF_A or OFF_B activate the PNP-NPN shutdown-latch, bringing down the 3.3V that came from the zener - down to something in the neighborhood of 1V. At that voltage, the common-base will be off or weak enough that the PMOS should be off (verify this!). The shutdown-latch should remain active until the 48V output node's capacitance is nearly emptied out.
- 
- Simplified(?):
- The second circuit assumes that once the MCU has turned off, everything is off and stays that way. Not entirely confident that would be the case. For instance if the "3.3V" node were at something like 2V when the MCU turns off, the OFF_A/OFF_B signals would tristate, and the common-base NPN could turn back on (albeit weakly), potentially restarting everything depending on the MCU's actual UVLO voltage.
- 
- immediate comments, going left to right in circuit:
- * C61 ... can form undamped LC with input wiring, and thus overshoot to nearly twice Vin on plugin (or more likely some V a bit above Vbr at which TVS and the cap together eat the inrush). If placed right at the input, consider higher V rating?
- * D3 5.0SMDJ64A ... max Vbr =~ 79V (not to speak of Vcl). This is vs Q1 Vds_max=80V
- * D9 placement no good, will always conduct
- * Q1 in general ... how much current is used? Can you tolerate just using a large diode?
- * QF2/Q7 ... does the 3v3 rail depend on this circuit's output? Without 3v3 being available, QF2/Q7 will never turn on
- * U10 ... when opto is on, it will defeat ability of U4/U9/QF2 to turn Q7 off
- * Q7 ... what's the rationale for the inner PMOS being different, and bigger, than the outer one?
- * U10/R59 ... are you sure 48V/100k = 480uA (nominal) will turn it on reliably enough?
- As to how to go about the latching functionality I'm reading from the description? TBH there are probably dedicated IC's for this, depending on the application. That aside, my thought would be to ensure that both the output node "+48V_SW" and the 3.3V node are thoroughly turned off.
- Below are two ideas for the latching startup/shutdown functionality, without addressing the reverse voltage or transient protection. The second one might be easier to start with for learning purposes.
- The first one has an implicit requirement, to keep the PMOS off until the +48V_SW node has been brought down even lower than the voltage at which the MCU would turn off.
- Turn-on: Everything is off until the switch has been pressed. The switch creates a temporary turn-on path for the PMOS gate, which raises the +48V output node. That in turn energizes the 3.3V zener, and from that, the common-base NPN turns on thru the 3.3k resistor, keeping the PMOS on without needing the switch any more. I'd consider a small cap parallel to the 3.3V zener, just for peace of mind vs transients on the 48V node.
- Turn-off: Logic signals OFF_A or OFF_B activate the PNP-NPN shutdown-latch, bringing down the 3.3V that came from the zener - down to something in the neighborhood of 1V. At that voltage, the common-base will be off or weak enough that the PMOS should be off (verify this!). The shutdown-latch should remain active until the 48V output node's capacitance is nearly emptied out.
- 
- Simplified(?):
- The second circuit assumes that once the MCU has turned off, everything is off and stays that way. Not entirely confident that would be the case. For instance if the "3.3V" node were at something like 2V when the MCU turns off, the OFF_A/OFF_B signals would tristate, and the common-base NPN could turn back on (albeit weakly), potentially restarting everything depending on the MCU's actual UVLO voltage.
- 
#5: Post edited
by
Pete W
·
2025-11-04T04:42:28Z (11 months ago)
- immediate comments, going left to right in circuit:
- * C61 ... can form undamped LC with input wiring, and thus overshoot to nearly twice Vin on plugin (or more likely some V a bit above Vbr at which TVS and the cap together eat the inrush). If placed right at the input, consider higher V rating?
- * D3 5.0SMDJ64A ... max Vbr =~ 79V (not to speak of Vcl). This is vs Q1 Vds_max=80V
- * D9 placement no good, will always conduct
- * Q1 in general ... how much current is used? Can you tolerate just using a large diode?
- * QF2/Q7 ... does the 3v3 rail depend on this circuit's output? Without 3v3 being available, QF2/Q7 will never turn on
- * U10 ... when opto is on, it will defeat ability of U4/U9/QF2 to turn Q7 off
- * Q7 ... what's the rationale for the inner PMOS being different, and bigger, than the outer one?
- * U10/R59 ... are you sure 48V/100k = 480uA (nominal) will turn it on reliably enough?
- * U10 doesn't seem to be doing much isolation anyway?
- As to how to go about the latching functionality I'm reading from the description? TBH there are probably dedicated IC's for this, depending on the application. That aside, my thought would be to ensure that both the output node "+48V_SW" and the 3.3V node are thoroughly turned off.
- Below are two ideas for the latching startup/shutdown functionality, without addressing the reverse voltage or transient protection. The second one might be easier to start with for learning purposes.
- The first one has an implicit requirement, to keep the PMOS off until the +48V_SW node has been brought down even lower than the voltage at which the MCU would turn off.
- Turn-on: Everything is off until the switch has been pressed. The switch creates a temporary turn-on path for the PMOS gate, which raises the +48V output node. That in turn energizes the 3.3V zener, and from that, the common-base NPN turns on thru the 3.3k resistor, keeping the PMOS on without needing the switch any more. I'd consider a small cap parallel to the 3.3V zener, just for peace of mind vs transients on the 48V node.
- Turn-off: Logic signals OFF_A or OFF_B activate the PNP-NPN shutdown-latch, bringing down the 3.3V that came from the zener - down to something in the neighborhood of 1V. At that voltage, the common-base will be off or weak enough that the PMOS should be off (verify this!). The shutdown-latch should remain active until the 48V output node's capacitance is nearly emptied out.
- Simplified(?):
- The second circuit assumes that once the MCU has turned off, everything is off and stays that way. Not entirely confident that would be the case. For instance if the "3.3V" node were at something like 2V when the MCU turns off, the OFF_A/OFF_B signals would tristate, and the common-base NPN could turn back on (albeit weakly), potentially restarting everything depending on the MCU's actual UVLO voltage.
- 
- immediate comments, going left to right in circuit:
- * C61 ... can form undamped LC with input wiring, and thus overshoot to nearly twice Vin on plugin (or more likely some V a bit above Vbr at which TVS and the cap together eat the inrush). If placed right at the input, consider higher V rating?
- * D3 5.0SMDJ64A ... max Vbr =~ 79V (not to speak of Vcl). This is vs Q1 Vds_max=80V
- * D9 placement no good, will always conduct
- * Q1 in general ... how much current is used? Can you tolerate just using a large diode?
- * QF2/Q7 ... does the 3v3 rail depend on this circuit's output? Without 3v3 being available, QF2/Q7 will never turn on
- * U10 ... when opto is on, it will defeat ability of U4/U9/QF2 to turn Q7 off
- * Q7 ... what's the rationale for the inner PMOS being different, and bigger, than the outer one?
- * U10/R59 ... are you sure 48V/100k = 480uA (nominal) will turn it on reliably enough?
- * U10 doesn't seem to be doing much isolation anyway?
- As to how to go about the latching functionality I'm reading from the description? TBH there are probably dedicated IC's for this, depending on the application. That aside, my thought would be to ensure that both the output node "+48V_SW" and the 3.3V node are thoroughly turned off.
- Below are two ideas for the latching startup/shutdown functionality, without addressing the reverse voltage or transient protection. The second one might be easier to start with for learning purposes.
- The first one has an implicit requirement, to keep the PMOS off until the +48V_SW node has been brought down even lower than the voltage at which the MCU would turn off.
- Turn-on: Everything is off until the switch has been pressed. The switch creates a temporary turn-on path for the PMOS gate, which raises the +48V output node. That in turn energizes the 3.3V zener, and from that, the common-base NPN turns on thru the 3.3k resistor, keeping the PMOS on without needing the switch any more. I'd consider a small cap parallel to the 3.3V zener, just for peace of mind vs transients on the 48V node.
- Turn-off: Logic signals OFF_A or OFF_B activate the PNP-NPN shutdown-latch, bringing down the 3.3V that came from the zener - down to something in the neighborhood of 1V. At that voltage, the common-base will be off or weak enough that the PMOS should be off (verify this!). The shutdown-latch should remain active until the 48V output node's capacitance is nearly emptied out.
- 
- Simplified(?):
- The second circuit assumes that once the MCU has turned off, everything is off and stays that way. Not entirely confident that would be the case. For instance if the "3.3V" node were at something like 2V when the MCU turns off, the OFF_A/OFF_B signals would tristate, and the common-base NPN could turn back on (albeit weakly), potentially restarting everything depending on the MCU's actual UVLO voltage.
- 
#4: Post edited
by
Pete W
·
2025-11-04T02:52:27Z (11 months ago)
- immediate comments, going left to right in circuit:
- * C61 ... can form undamped LC with input wiring, and thus overshoot to nearly twice Vin on plugin (or more likely some V a bit above Vbr at which TVS and the cap together eat the inrush). If placed right at the input, consider higher V rating?
- * D3 5.0SMDJ64A ... max Vbr =~ 79V (not to speak of Vcl). This is vs Q1 Vds_max=80V
- * D9 placement no good, will always conduct
- * Q1 in general ... how much current is used? Can you tolerate just using a large diode?
- * QF2/Q7 ... does the 3v3 rail depend on this circuit's output? Without 3v3 being available, QF2/Q7 will never turn on
- * U10 ... when opto is on, it will defeat ability of U4/U9/QF2 to turn Q7 off
- * Q7 ... what's the rationale for the inner PMOS being different, and bigger, than the outer one?
- * U10/R59 ... are you sure 48V/100k = 480uA (nominal) will turn it on reliably enough?
- * U10 doesn't seem to be doing much isolation anyway?
- As to how to go about the latching functionality I'm reading from the description? TBH there are probably dedicated IC's for this, depending on the application. That aside, my thought would be to ensure that both the output node "+48V_SW" and the 3.3V node are thoroughly turned off.
Below are two ideas for the latching startup/shutdown functionality, without addressing the reverse voltage or transient protection.- The first one has an implicit requirement, to keep the PMOS off until the +48V_SW node has been brought down even lower than the voltage at which the MCU would turn off.
- Turn-on: Everything is off until the switch has been pressed. The switch creates a temporary turn-on path for the PMOS gate, which raises the +48V output node. That in turn energizes the 3.3V zener, and from that, the common-base NPN turns on thru the 3.3k resistor, keeping the PMOS on without needing the switch any more. I'd consider a small cap parallel to the 3.3V zener, just for peace of mind vs transients on the 48V node.
- Turn-off: Logic signals OFF_A or OFF_B activate the PNP-NPN shutdown-latch, bringing down the 3.3V that came from the zener - down to something in the neighborhood of 1V. At that voltage, the common-base will be off or weak enough that the PMOS should be off (verify this!). The shutdown-latch should remain active until the 48V output node's capacitance is nearly emptied out.
- 
- Simplified(?):
- The second circuit assumes that once the MCU has turned off, everything is off and stays that way. Not entirely confident that would be the case. For instance if the "3.3V" node were at something like 2V when the MCU turns off, the OFF_A/OFF_B signals would tristate, and the common-base NPN could turn back on (albeit weakly), potentially restarting everything depending on the MCU's actual UVLO voltage.
- 
- immediate comments, going left to right in circuit:
- * C61 ... can form undamped LC with input wiring, and thus overshoot to nearly twice Vin on plugin (or more likely some V a bit above Vbr at which TVS and the cap together eat the inrush). If placed right at the input, consider higher V rating?
- * D3 5.0SMDJ64A ... max Vbr =~ 79V (not to speak of Vcl). This is vs Q1 Vds_max=80V
- * D9 placement no good, will always conduct
- * Q1 in general ... how much current is used? Can you tolerate just using a large diode?
- * QF2/Q7 ... does the 3v3 rail depend on this circuit's output? Without 3v3 being available, QF2/Q7 will never turn on
- * U10 ... when opto is on, it will defeat ability of U4/U9/QF2 to turn Q7 off
- * Q7 ... what's the rationale for the inner PMOS being different, and bigger, than the outer one?
- * U10/R59 ... are you sure 48V/100k = 480uA (nominal) will turn it on reliably enough?
- * U10 doesn't seem to be doing much isolation anyway?
- As to how to go about the latching functionality I'm reading from the description? TBH there are probably dedicated IC's for this, depending on the application. That aside, my thought would be to ensure that both the output node "+48V_SW" and the 3.3V node are thoroughly turned off.
- Below are two ideas for the latching startup/shutdown functionality, without addressing the reverse voltage or transient protection. The second one might be easier to start with for learning purposes.
- The first one has an implicit requirement, to keep the PMOS off until the +48V_SW node has been brought down even lower than the voltage at which the MCU would turn off.
- Turn-on: Everything is off until the switch has been pressed. The switch creates a temporary turn-on path for the PMOS gate, which raises the +48V output node. That in turn energizes the 3.3V zener, and from that, the common-base NPN turns on thru the 3.3k resistor, keeping the PMOS on without needing the switch any more. I'd consider a small cap parallel to the 3.3V zener, just for peace of mind vs transients on the 48V node.
- Turn-off: Logic signals OFF_A or OFF_B activate the PNP-NPN shutdown-latch, bringing down the 3.3V that came from the zener - down to something in the neighborhood of 1V. At that voltage, the common-base will be off or weak enough that the PMOS should be off (verify this!). The shutdown-latch should remain active until the 48V output node's capacitance is nearly emptied out.
- 
- Simplified(?):
- The second circuit assumes that once the MCU has turned off, everything is off and stays that way. Not entirely confident that would be the case. For instance if the "3.3V" node were at something like 2V when the MCU turns off, the OFF_A/OFF_B signals would tristate, and the common-base NPN could turn back on (albeit weakly), potentially restarting everything depending on the MCU's actual UVLO voltage.
- 
#3: Post edited
by
Pete W
·
2025-11-04T02:41:43Z (11 months ago)
- immediate comments, going left to right in circuit:
- * C61 ... can form undamped LC with input wiring, and thus overshoot to nearly twice Vin on plugin (or more likely some V a bit above Vbr at which TVS and the cap together eat the inrush). If placed right at the input, consider higher V rating?
- * D3 5.0SMDJ64A ... max Vbr =~ 79V (not to speak of Vcl). This is vs Q1 Vds_max=80V
- * D9 placement no good, will always conduct
- * Q1 in general ... how much current is used? Can you tolerate just using a large diode?
- * QF2/Q7 ... does the 3v3 rail depend on this circuit's output? Without 3v3 being available, QF2/Q7 will never turn on
- * U10 ... when opto is on, it will defeat ability of U4/U9/QF2 to turn Q7 off
- * Q7 ... what's the rationale for the inner PMOS being different, and bigger, than the outer one?
- * U10/R59 ... are you sure 48V/100k = 480uA (nominal) will turn it on reliably enough?
- * U10 doesn't seem to be doing much isolation anyway?
- As to how to go about the latching functionality I'm reading from the description? TBH there are probably dedicated IC's for this, depending on the application. That aside, my thought would be to ensure that both the output node "+48V_SW" and the 3.3V node are thoroughly turned off.
- Below are two ideas for the latching startup/shutdown functionality, without addressing the reverse voltage or transient protection.
- The first one has an implicit requirement, to keep the PMOS off until the +48V_SW node has been brought down even lower than the voltage at which the MCU would turn off.
- Turn-on: Everything is off until the switch has been pressed. The switch creates a temporary turn-on path for the PMOS gate, which raises the +48V output node. That in turn energizes the 3.3V zener, and from that, the common-base NPN turns on thru the 3.3k resistor, keeping the PMOS on without needing the switch any more. I'd consider a small cap parallel to the 3.3V zener, just for peace of mind vs transients on the 48V node.
- Turn-off: Logic signals OFF_A or OFF_B activate the PNP-NPN shutdown-latch, bringing down the 3.3V that came from the zener - down to something in the neighborhood of 1V. At that voltage, the common-base will be off or weak enough that the PMOS should be off (verify this!). The shutdown-latch should remain active until the 48V output node's capacitance is nearly emptied out.
- 
- Simplified(?):
The second circuit assumes that once the MCU has turned off, everything is off and stays that way. Not entirely confident that would be the case. For instance if the "3.3V" node were at something like 2V when the MCU turns off, the OFF_A/OFF_B signals would tristate, and the common-base NPN could turn back on (albeit weakly), potentially restarting everything.- 
- immediate comments, going left to right in circuit:
- * C61 ... can form undamped LC with input wiring, and thus overshoot to nearly twice Vin on plugin (or more likely some V a bit above Vbr at which TVS and the cap together eat the inrush). If placed right at the input, consider higher V rating?
- * D3 5.0SMDJ64A ... max Vbr =~ 79V (not to speak of Vcl). This is vs Q1 Vds_max=80V
- * D9 placement no good, will always conduct
- * Q1 in general ... how much current is used? Can you tolerate just using a large diode?
- * QF2/Q7 ... does the 3v3 rail depend on this circuit's output? Without 3v3 being available, QF2/Q7 will never turn on
- * U10 ... when opto is on, it will defeat ability of U4/U9/QF2 to turn Q7 off
- * Q7 ... what's the rationale for the inner PMOS being different, and bigger, than the outer one?
- * U10/R59 ... are you sure 48V/100k = 480uA (nominal) will turn it on reliably enough?
- * U10 doesn't seem to be doing much isolation anyway?
- As to how to go about the latching functionality I'm reading from the description? TBH there are probably dedicated IC's for this, depending on the application. That aside, my thought would be to ensure that both the output node "+48V_SW" and the 3.3V node are thoroughly turned off.
- Below are two ideas for the latching startup/shutdown functionality, without addressing the reverse voltage or transient protection.
- The first one has an implicit requirement, to keep the PMOS off until the +48V_SW node has been brought down even lower than the voltage at which the MCU would turn off.
- Turn-on: Everything is off until the switch has been pressed. The switch creates a temporary turn-on path for the PMOS gate, which raises the +48V output node. That in turn energizes the 3.3V zener, and from that, the common-base NPN turns on thru the 3.3k resistor, keeping the PMOS on without needing the switch any more. I'd consider a small cap parallel to the 3.3V zener, just for peace of mind vs transients on the 48V node.
- Turn-off: Logic signals OFF_A or OFF_B activate the PNP-NPN shutdown-latch, bringing down the 3.3V that came from the zener - down to something in the neighborhood of 1V. At that voltage, the common-base will be off or weak enough that the PMOS should be off (verify this!). The shutdown-latch should remain active until the 48V output node's capacitance is nearly emptied out.
- 
- Simplified(?):
- The second circuit assumes that once the MCU has turned off, everything is off and stays that way. Not entirely confident that would be the case. For instance if the "3.3V" node were at something like 2V when the MCU turns off, the OFF_A/OFF_B signals would tristate, and the common-base NPN could turn back on (albeit weakly), potentially restarting everything depending on the MCU's actual UVLO voltage.
- 
#2: Post edited
by
Pete W
·
2025-11-04T02:40:55Z (11 months ago)
- immediate comments, going left to right in circuit:
- * C61 ... can form undamped LC with input wiring, and thus overshoot to nearly twice Vin on plugin (or more likely some V a bit above Vbr at which TVS and the cap together eat the inrush). If placed right at the input, consider higher V rating?
- * D3 5.0SMDJ64A ... max Vbr =~ 79V (not to speak of Vcl). This is vs Q1 Vds_max=80V
- * D9 placement no good, will always conduct
- * Q1 in general ... how much current is used? Can you tolerate just using a large diode?
- * QF2/Q7 ... does the 3v3 rail depend on this circuit's output? Without 3v3 being available, QF2/Q7 will never turn on
- * U10 ... when opto is on, it will defeat ability of U4/U9/QF2 to turn Q7 off
- * Q7 ... what's the rationale for the inner PMOS being different, and bigger, than the outer one?
- * U10/R59 ... are you sure 48V/100k = 480uA (nominal) will turn it on reliably enough?
- * U10 doesn't seem to be doing much isolation anyway?
- As to how to go about the latching functionality I'm reading from the description? TBH there are probably dedicated IC's for this, depending on the application. That aside, my thought would be to ensure that both the output node "+48V_SW" and the 3.3V node are thoroughly turned off.
- Below are two ideas for the latching startup/shutdown functionality, without addressing the reverse voltage or transient protection.
- The first one has an implicit requirement, to keep the PMOS off until the +48V_SW node has been brought down even lower than the voltage at which the MCU would turn off.
- Turn-on: Everything is off until the switch has been pressed. The switch creates a temporary turn-on path for the PMOS gate, which raises the +48V output node. That in turn energizes the 3.3V zener, and from that, the common-base NPN turns on thru the 3.3k resistor, keeping the PMOS on without needing the switch any more. I'd consider a small cap parallel to the 3.3V zener, just for peace of mind vs transients on the 48V node.
- Turn-off: Logic signals OFF_A or OFF_B activate the PNP-NPN shutdown-latch, bringing down the 3.3V that came from the zener - down to something in the neighborhood of 1V. At that voltage, the common-base will be off or weak enough that the PMOS should be off (verify this!). The shutdown-latch should remain active until the 48V output node's capacitance is nearly emptied out.
- 
- Simplified(?):
The second circuit assumes that once the MCU has turned off, everything is off and stays that way. Not entirely confident that would be the case. For instance if the "3.3V" node were at something like 2V when the MCU turns off, the OFF_A/OFF_B signals would tristate, and the common-base NPN could turn back on (albeit weakly), potentially restarting everything. Included it just for the conceptual value.- 
- immediate comments, going left to right in circuit:
- * C61 ... can form undamped LC with input wiring, and thus overshoot to nearly twice Vin on plugin (or more likely some V a bit above Vbr at which TVS and the cap together eat the inrush). If placed right at the input, consider higher V rating?
- * D3 5.0SMDJ64A ... max Vbr =~ 79V (not to speak of Vcl). This is vs Q1 Vds_max=80V
- * D9 placement no good, will always conduct
- * Q1 in general ... how much current is used? Can you tolerate just using a large diode?
- * QF2/Q7 ... does the 3v3 rail depend on this circuit's output? Without 3v3 being available, QF2/Q7 will never turn on
- * U10 ... when opto is on, it will defeat ability of U4/U9/QF2 to turn Q7 off
- * Q7 ... what's the rationale for the inner PMOS being different, and bigger, than the outer one?
- * U10/R59 ... are you sure 48V/100k = 480uA (nominal) will turn it on reliably enough?
- * U10 doesn't seem to be doing much isolation anyway?
- As to how to go about the latching functionality I'm reading from the description? TBH there are probably dedicated IC's for this, depending on the application. That aside, my thought would be to ensure that both the output node "+48V_SW" and the 3.3V node are thoroughly turned off.
- Below are two ideas for the latching startup/shutdown functionality, without addressing the reverse voltage or transient protection.
- The first one has an implicit requirement, to keep the PMOS off until the +48V_SW node has been brought down even lower than the voltage at which the MCU would turn off.
- Turn-on: Everything is off until the switch has been pressed. The switch creates a temporary turn-on path for the PMOS gate, which raises the +48V output node. That in turn energizes the 3.3V zener, and from that, the common-base NPN turns on thru the 3.3k resistor, keeping the PMOS on without needing the switch any more. I'd consider a small cap parallel to the 3.3V zener, just for peace of mind vs transients on the 48V node.
- Turn-off: Logic signals OFF_A or OFF_B activate the PNP-NPN shutdown-latch, bringing down the 3.3V that came from the zener - down to something in the neighborhood of 1V. At that voltage, the common-base will be off or weak enough that the PMOS should be off (verify this!). The shutdown-latch should remain active until the 48V output node's capacitance is nearly emptied out.
- 
- Simplified(?):
- The second circuit assumes that once the MCU has turned off, everything is off and stays that way. Not entirely confident that would be the case. For instance if the "3.3V" node were at something like 2V when the MCU turns off, the OFF_A/OFF_B signals would tristate, and the common-base NPN could turn back on (albeit weakly), potentially restarting everything.
- 
#1: Post edited
by
Pete W
·
2025-11-04T02:40:35Z (11 months ago)
- immediate comments, going left to right in circuit:
- * C61 ... can form undamped LC with input wiring, and thus overshoot to nearly twice Vin on plugin (or more likely some V a bit above Vbr at which TVS and the cap together eat the inrush). If placed right at the input, consider higher V rating?
- * D3 5.0SMDJ64A ... max Vbr =~ 79V (not to speak of Vcl). This is vs Q1 Vds_max=80V
- * D9 placement no good, will always conduct
- * Q1 in general ... how much current is used? Can you tolerate just using a large diode?
- * QF2/Q7 ... does the 3v3 rail depend on this circuit's output? Without 3v3 being available, QF2/Q7 will never turn on
- * U10 ... when opto is on, it will defeat ability of U4/U9/QF2 to turn Q7 off
- * Q7 ... what's the rationale for the inner PMOS being different, and bigger, than the outer one?
- * U10/R59 ... are you sure 48V/100k = 480uA (nominal) will turn it on reliably enough?
- * U10 doesn't seem to be doing much isolation anyway?
- As to how to go about the latching functionality I'm reading from the description? TBH there are probably dedicated IC's for this, depending on the application. That aside, my thought would be to ensure that both the output node "+48V_SW" and the 3.3V node are thoroughly turned off.
- Below are two ideas for the latching startup/shutdown functionality, without addressing the reverse voltage or transient protection.
- The first one has an implicit requirement, to keep the PMOS off until the +48V_SW node has been brought down even lower than the voltage at which the MCU would turn off.
- Turn-on: Everything is off until the switch has been pressed. The switch creates a temporary turn-on path for the PMOS gate, which raises the +48V output node. That in turn energizes the 3.3V zener, and from that, the common-base NPN turns on thru the 3.3k resistor, keeping the PMOS on without needing the switch any more. I'd consider a small cap parallel to the 3.3V zener, just for peace of mind vs transients on the 48V node.
- Turn-off: Logic signals OFF_A or OFF_B activate the PNP-NPN shutdown-latch, bringing down the 3.3V that came from the zener - down to something in the neighborhood of 1V. At that voltage, the common-base will be off or weak enough that the PMOS should be off (verify this!). The shutdown-latch should remain active until the 48V output node's capacitance is nearly emptied out.
- 
- Simplified(?):
The second circuit assumes that once the MCU has turned off, everything is off and stays that way. Not entirely confident that would be the case. For instance if the "3.3V" node were at something like 2V when the MCU turns off, the OFF_A/OFF_B signals would tristate, and the common-base NPN would turn back on, potentially restarting everything unintentionally. Included it just for the conceptual value.- 
- immediate comments, going left to right in circuit:
- * C61 ... can form undamped LC with input wiring, and thus overshoot to nearly twice Vin on plugin (or more likely some V a bit above Vbr at which TVS and the cap together eat the inrush). If placed right at the input, consider higher V rating?
- * D3 5.0SMDJ64A ... max Vbr =~ 79V (not to speak of Vcl). This is vs Q1 Vds_max=80V
- * D9 placement no good, will always conduct
- * Q1 in general ... how much current is used? Can you tolerate just using a large diode?
- * QF2/Q7 ... does the 3v3 rail depend on this circuit's output? Without 3v3 being available, QF2/Q7 will never turn on
- * U10 ... when opto is on, it will defeat ability of U4/U9/QF2 to turn Q7 off
- * Q7 ... what's the rationale for the inner PMOS being different, and bigger, than the outer one?
- * U10/R59 ... are you sure 48V/100k = 480uA (nominal) will turn it on reliably enough?
- * U10 doesn't seem to be doing much isolation anyway?
- As to how to go about the latching functionality I'm reading from the description? TBH there are probably dedicated IC's for this, depending on the application. That aside, my thought would be to ensure that both the output node "+48V_SW" and the 3.3V node are thoroughly turned off.
- Below are two ideas for the latching startup/shutdown functionality, without addressing the reverse voltage or transient protection.
- The first one has an implicit requirement, to keep the PMOS off until the +48V_SW node has been brought down even lower than the voltage at which the MCU would turn off.
- Turn-on: Everything is off until the switch has been pressed. The switch creates a temporary turn-on path for the PMOS gate, which raises the +48V output node. That in turn energizes the 3.3V zener, and from that, the common-base NPN turns on thru the 3.3k resistor, keeping the PMOS on without needing the switch any more. I'd consider a small cap parallel to the 3.3V zener, just for peace of mind vs transients on the 48V node.
- Turn-off: Logic signals OFF_A or OFF_B activate the PNP-NPN shutdown-latch, bringing down the 3.3V that came from the zener - down to something in the neighborhood of 1V. At that voltage, the common-base will be off or weak enough that the PMOS should be off (verify this!). The shutdown-latch should remain active until the 48V output node's capacitance is nearly emptied out.
- 
- Simplified(?):
- The second circuit assumes that once the MCU has turned off, everything is off and stays that way. Not entirely confident that would be the case. For instance if the "3.3V" node were at something like 2V when the MCU turns off, the OFF_A/OFF_B signals would tristate, and the common-base NPN could turn back on (albeit weakly), potentially restarting everything. Included it just for the conceptual value.
- 