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ADE7933 layout guidelines - Lazy Y capacitor?

[ADE7933](https://www.analog.com/media/en/technical-documentation/data-sheets/ade7978_7933_7932_7923.pdf) contains an isolated DC-DC converter (Page 82). The control uses ~1MHz PWM signal with unknown rise time, but assuming something like 10ns, most of the energy would be contained in the 35MHz band based on:

$f_{\text{max}} \approx \frac{0.35}{t_r} \approx \frac{0.35}{10 \times 10^{-9}} = 35\,\text{MHz}$


Knowing that the winding capacitance can cause common mode noise issues, a 'Y' capacitor is often added between the windings to provide return path for the common mode current back to primary. However, this datasheet suggests to use PCB itself to create the same effect (Page 92):

![Image_alt_text](https://electrical.codidact.com/uploads/0btj1bh2rae51m9aqbpa9a73uvy0)

This seems like a 'lazy' Y capacitor that is heavily dependent on the layout around the board to form this interplanar capacitance between primary and secondary. The value is not possible to tune. It also seems that this has to be extensively documented, since if the stackup was to change, this could introduce a safety risk. What I am wondering is why go through all this, if a discrete component can achieve the same performance? Are there any advantages of this approach besides saving cents on a discrete Y capacitor?