Post History
Planar Loop has the minimum depth (~ a few µm) and therefore would produce the highest parasitic inductance. Vertical Loop 1 is on a 2-layer PCB and its depth is the height of the PCB (~ a few mm...
#3: Post edited
by
Andy aka
·
2026-03-03T14:00:30Z (7 months ago)
> _Planar Loop has the minimum depth (~ a few µm) and therefore would produce the highest parasitic inductance. Vertical Loop 1 is on a 2-layer PCB and its depth is the height of the PCB (~ a few mm), therefore, its parasitic inductance would be much lesser than the planar's. Vertical Loop 2 is on a 4-layer PCB and its depth is roughly 14 of vertical loop 1's, therefore its inductance will be smaller than vertical loop 1's (refer screenshot 4 and 5 below)._The above appears to be where you are introducing much confusion. For a start, the depth of the loop being smaller means less parasitic inductance yet, you appear to be saying it would produce the highest parasitic inductance. This is wrong.- Then you assert that vertical loop 1 (based on a two-layer PCB) would have less inductance. This is also wrong.
- Then you say that vertical loop 2 has a depth of 14 times vertical loop 1's depth and clearly this is nonsensical. I think you meant to say 1/4 rather than 14 of course.
- The bottom line is that a loop that has a smaller aperture area will have less parasitic inductance compared to one with a bigger aperture. And, the loop with the larger conductor "**width**" will also have less inductance.
- By "**width**" I'm referring to the width of the PCB trace. What you refer to as depth appears to be at odds with conventional wisdom as portrayed in your second image entitled "screenshot 2". Please stick to conventions.
- > _Planar Loop has the minimum depth (~ a few µm) and therefore would produce the **highest** parasitic inductance. Vertical Loop 1 is on a 2-layer PCB and its depth is the height of the PCB (~ a few mm), therefore, its parasitic inductance would be much lesser than the planar's. Vertical Loop 2 is on a 4-layer PCB and its depth is roughly 14 of vertical loop 1's, therefore its inductance will be smaller than vertical loop 1's (refer screenshot 4 and 5 below)._
- The above appears to be where you are introducing much confusion. For a start, the depth of the planar loop being smaller means **less** parasitic inductance yet, you appear to be saying it would produce the **highest** parasitic inductance. This is wrong.
- Then you assert that vertical loop 1 (based on a two-layer PCB) would have less inductance. This is also wrong.
- Then you say that vertical loop 2 has a depth of 14 times vertical loop 1's depth and clearly this is nonsensical. I think you meant to say 1/4 rather than 14 of course.
- The bottom line is that a loop that has a smaller aperture area will have less parasitic inductance compared to one with a bigger aperture. And, the loop with the larger conductor "**width**" will also have less inductance.
- By "**width**" I'm referring to the width of the PCB trace. What you refer to as depth appears to be at odds with conventional wisdom as portrayed in your second image entitled "screenshot 2". Please stick to conventions.
#2: Post edited
by
Andy aka
·
2026-03-03T13:58:20Z (7 months ago)
- > _Planar Loop has the minimum depth (~ a few µm) and therefore would produce the highest parasitic inductance. Vertical Loop 1 is on a 2-layer PCB and its depth is the height of the PCB (~ a few mm), therefore, its parasitic inductance would be much lesser than the planar's. Vertical Loop 2 is on a 4-layer PCB and its depth is roughly 14 of vertical loop 1's, therefore its inductance will be smaller than vertical loop 1's (refer screenshot 4 and 5 below)._
- The above appears to be where you are introducing much confusion. For a start, the depth of the loop being smaller means less parasitic inductance yet, you appear to be saying it would produce the highest parasitic inductance. This is wrong.
- Then you assert that vertical loop 1 (based on a two-layer PCB) would have less inductance. This is also wrong.
- Then you say that vertical loop 2 has a depth of 14 times vertical loop 1's depth and clearly this is nonsensical. I think you meant to say 1/4 rather than 14 of course.
The bottom line is that a loop that has a smaller aperture area will have less parasitic inductance compared to one with a bigger aperture. And, the loop with the widest conductor will also have less inductance.
- > _Planar Loop has the minimum depth (~ a few µm) and therefore would produce the highest parasitic inductance. Vertical Loop 1 is on a 2-layer PCB and its depth is the height of the PCB (~ a few mm), therefore, its parasitic inductance would be much lesser than the planar's. Vertical Loop 2 is on a 4-layer PCB and its depth is roughly 14 of vertical loop 1's, therefore its inductance will be smaller than vertical loop 1's (refer screenshot 4 and 5 below)._
- The above appears to be where you are introducing much confusion. For a start, the depth of the loop being smaller means less parasitic inductance yet, you appear to be saying it would produce the highest parasitic inductance. This is wrong.
- Then you assert that vertical loop 1 (based on a two-layer PCB) would have less inductance. This is also wrong.
- Then you say that vertical loop 2 has a depth of 14 times vertical loop 1's depth and clearly this is nonsensical. I think you meant to say 1/4 rather than 14 of course.
- The bottom line is that a loop that has a smaller aperture area will have less parasitic inductance compared to one with a bigger aperture. And, the loop with the larger conductor "**width**" will also have less inductance.
- By "**width**" I'm referring to the width of the PCB trace. What you refer to as depth appears to be at odds with conventional wisdom as portrayed in your second image entitled "screenshot 2". Please stick to conventions.
#1: Initial revision
by
Andy aka
·
2026-03-03T13:55:18Z (7 months ago)
> _Planar Loop has the minimum depth (~ a few µm) and therefore would produce the highest parasitic inductance. Vertical Loop 1 is on a 2-layer PCB and its depth is the height of the PCB (~ a few mm), therefore, its parasitic inductance would be much lesser than the planar's. Vertical Loop 2 is on a 4-layer PCB and its depth is roughly 14 of vertical loop 1's, therefore its inductance will be smaller than vertical loop 1's (refer screenshot 4 and 5 below)._ The above appears to be where you are introducing much confusion. For a start, the depth of the loop being smaller means less parasitic inductance yet, you appear to be saying it would produce the highest parasitic inductance. This is wrong. Then you assert that vertical loop 1 (based on a two-layer PCB) would have less inductance. This is also wrong. Then you say that vertical loop 2 has a depth of 14 times vertical loop 1's depth and clearly this is nonsensical. I think you meant to say 1/4 rather than 14 of course. The bottom line is that a loop that has a smaller aperture area will have less parasitic inductance compared to one with a bigger aperture. And, the loop with the widest conductor will also have less inductance.