Post History

Can the via-in-pad (VIP) get damaged due to hand soldering during rework?

**Background:** I have already posted my [question](https://electronics.stackexchange.com/questions/770698/can-the-vias-of-via-in-pad-get-damaged-due-to-hand-soldering-while-rework) on electronics.stackexchange.com (EESE) and I did get an [answer](https://electronics.stackexchange.com/a/770716/344652) too. However, I am not satisfied by the explanation so far.

**Literature survey done till now:** I have gone through questions on such as [question 1](https://electronics.stackexchange.com/questions/170209/anything-bad-to-place-a-via-on-a-pad?noredirect=1&lq=1) and [question 2](https://electronics.stackexchange.com/questions/39287/vias-directly-on-smd-pads) on EESE. I have also gone through discussions on reddit such as [reddit discussion 1](https://www.reddit.com/r/AskElectronics/comments/1pwjq8c/placed_vias_directly_in_pads_for_08051206/) and [reddit discussion 2](https://www.reddit.com/r/PrintedCircuitBoard/comments/m3j9uz/how_bad_is_it_to_put_a_via_on_the_center_of_an/). I found a few discussions on eev forum blog too such as [eev discussion 1](https://www.eevblog.com/forum/beginners/via-in-pad-371534/), [eev discussion 2](https://www.eevblog.com/forum/projects/via-in-pad/), and [eev discussion 3](https://www.eevblog.com/forum/projects/vias-on-pads/).

From the literature survey I concluded:

1) Much of the discussion on via-in-pad (VIP) was either about heat dissipation for ICs in BGA package or QFN package. Or, from the perspective of soldering, mainly reflow (what can possibly go wrong while soldering components on top of these vias). Not much discussion was about VIPs and hand soldering.
2) People have mixed opinion about VIP. Some favour it and encourgae others to use it, while many oppose it and advice the same to others.
3) The engineering community is clearly divided about VIPs.


**My Question:**
To minimize the routing complexity on my PCB (*2 different designs, each with 12 (+5) and 20 (+9) MOSFETs (+diodes) respectively along with their individual isolated power supplies*), I intend to use the VIP (vias of 0.3 mm diameter) concept for laying down my PWM tracks. The final layout is not complete yet, however, I have shared a tentative idea of the layout approach that I have in my mind [using the screenshot uploaded in this link](https://i.sstatic.net/6HN9KbbB.png) (for some reason I am failing to upload the image). I have attached the [3d image top](https://i.sstatic.net/O2HDe418.png) and [3d image bottom](https://i.sstatic.net/UTJPf5ED.png) of the layout too. The resistors $R\_G\_Q\_L1$ (gate resistor) and $R\_GPD\_Q\_L1$ (pull down resistor) will be of 2512 package. $R\_G\_Q\_L1$ is not optimized yet. Therefore, based on measurements,  it will be changed as many times as needed, which implies the VIPs will also experience the same amount of heat as the pads themselves. I am a beginner to SMD soldering, in fact, I am not too good with through-hole soldering either. I am willing to learn and upskill myself though. 

My questions to the experienced engineers here are:

1) Is it okay for a beginner to work with VIPs?
2) Can the via-in-pads get damaged due to the heat of the iron during repeated rework?
3) Is via plugging (using plate over or epoxy or any other method) necessary for such a trivial application?
4) At 0.3 mm via hole with hand soldering, apart from solder melting through the holes, what else may possibly go wrong in this approach?
5) Any other advice/precaution that you think benefit me is also welcome.

I look forward to insightful and in depth answers and opinions from the experts.