The purpose is reverse polarity protection, but without context I can't say why they need 2 of them. Maybe some standard requiring redundancy. Or maybe the mechanics means that the gates aren't necessarily directly connected to each other in case a battery cell is put in reverse.

The reference documentation mentions a single MOSFET:

"Immediately following the battery is a low RDS_ON P-channel MOSFET and a bulk capacitor. The P-channel MOSFET prevents damage to the hardware if the coin cell battery is inserted backwards while minimizing the forward voltage drop in normal operation."

I feel that the extra MOSFET was an addition after some testing and measurement of early samples. The schematic shows that it's revision E1 for the initial release, so there were possibly four prior revisions before the board was RTM. I wonder if they found some corner case that necessitated the extra MOSFET and didn't update the design guide - maybe excessive leakage with the coin cell reversed, or the Rds_on was too low for the amount of caps on the rail and doubling-up the MOSFET was easier than sourcing a new part with higher Rds_on?

Coin cell batteries have pretty high ESR to begin with (much higher than the MOSFET Rds(on)) so I don't think they are even capable of creating a big inrush current when charging up the caps?

https://www.embedded.com/ul-coin-cell-requirements/

May I know Any relation with this