How to calculate pullup resistor value for pushbutton?
To understand this issue, we have to look at how your circuit works and what the pullup does within it.
You have a pushbutton you want to read with a microcontroller. The pushbutton is a momentary SPST (Single Pole Single Throw) switch. It has two connection points which are either connected or not. When the button is pressed, the two points are connected (switch is closed). When released, they are not connected (switch is open). Microcontrollers don't inherently detect connection or disconnection. What they do sense is a voltage. Since this switch has only two states it makes sense to use a digital input, which is after all designed to be in only one of two states. The micro can sense which state a digital input is in directly.
A pullup converts the open/closed connection of the switch to a low or high voltage the microcontroller can sense. Without a pullup, when the switch is pressed, the line is forced low because the switch essentially shorts it to ground. However, when the switch is released, nothing is driving the line to any particular voltage. It could just stay low, pick up other nearby signals by capacitive coupling, or eventually float to a specific voltage due to the tiny bit of leakage current thru the digital input. The job of the pullup resistor is to provide a positive guaranteed high level when the switch is open, but still allow the switch to safely short the line to ground when closed.
There are two main competing requirements on the size of the pullup resistor. It has to be low enough to solidly pull the line high, but high enough to not cause too much current to flow when the switch is closed. Both those are obviosly subjective and their relative importance depends on the situation. In general, you make the pullup just low enough to make sure the line is high when the switch is open, given all the things that might make the line low otherwise.
Let's look at what it takes to pull up the line. Looking only at the DC requirement uncovers the leakage current of the digital input line. The ideal digital input has infinite impedance. Real ones don't, of course, and the extent CMOS inputs are not ideal is usually expressed as a maximum leakage current that can either come out of or go into the pin. Let's say your micro is specified for 1 µA maximum leakage on its digital input pins. Since the pullup has to keep the line high, the worst case is assuming the pin looks like a 1 µA current sink to ground. If you were to use a 1 MΩ pullup, for example, then that 1 µA would cause 1 Volt accross the 1 MΩ resistor. Let's say this is a 5V system, so that means the pin is only guaranteed to be up to 4V. Now you have to look at the digital input spec and see what the minimum voltage requirement is for a logic high level. That can be 80% of Vdd for some micros, which would be 4V in this case. Therefore a 1 MΩ pullup is right at the margin. You need at least a little less than that for guaranteed correct behaviour due to DC considerations.
However, there are other considerations, and these are harder to quantify. Every node has some capacitive coupling to all other nodes, although the magnitude of that coupling falls off with distance such that only nearby nodes are relevant. If these other nodes have signals on them, these signals could couple onto your digital input. A lower value pullup makes the line lower impedance, which reduces the amount of stray signal it will pick up. It also gives you a higher minimum guaranteed DC level against the leakage current, so there is more room between that DC level and where the digital input might interpret the result as a logic low instead of the intended logic high. So how much is enough? Clearly the 1 MΩ pullup in this example is not enough (too high a resistance). It's nearly impossible to guess coupling to nearby signals, but I'd want at least an order of magnitude margin over the minimum DC case. That means I want a 100 kΩ pullup or lower, although if there is much noise around I'd want it to be lower.
There is another consideration driving the pullup lower, and that is rise time. The line will have some stray capacitance to ground, so will exponentially decay towards the supply value instead of instantly going there. Let's say all the stray capacitance adds up to 20 pF. That times the 100 kΩ pullup is 2 µs. It takes 3 time constants to get to 95% of the settling value, or 6 µs in this case. That is of no consequence in human time so doesn't matter in this example, but if this were a digital bus line you wanted to run at 400 kHz data rate, it wouldn't work.
Now lets look at the other competing consideration, which is the current wasted when the switch is pressed. If this unit is running off of line power or otherwise handling substantial power, a few mA won't matter. At 5V it takes 5 kΩ to draw 1 mA. That's actually "a lot" of current in some cases, and well more than required due to the other considerations. If this is a battery powered device and the switch could be on for a substantial fraction of the time, then every µA may matter and you have to think about this very carefully. In some cases you might sample the switch periodically and only turn on the pullup for a short time around the sample to minimize current draw.
Some switches also work better or have longer life when there is some minimum current when on. For small pushbuttons, this is usually below 1 mA.
Other than special considerations like battery operation, 100 kΩ is high enough impedance to make me nervous about picking up noise. 1 mA of current wasted when the switch is on seems unnecessarily large. So 500 µA, which means 10 kΩ impedance is about right for "ordinary" cases.
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Figuratively speaking, Olin Lathrop's answer is a wonderful story about the unequal "tug of war" between a "pulling up" resistor and "pulling down" switch. And, when the switch is 'off', the "struggle" is between the resistor and input leakages… and then the resistor must win.
To be more precise, the positive terminal of the power supply is what "pulls up" the common node through the resistor and the negative terminal "pulls down" it (either through the switch or leakages).
This arrangement is the same "voltage divider configuration", widely used in simple common-source logic gates with resistor load… and the considerations are the same.
In my teaching practice, I have observed that students find it difficult to understand that the voltage after the resistor (open circuit) should be almost equal to the supply voltage. When I ask how much this voltage is, I receive all sorts of answers - 0, 1/2 power supply and, most rarely, the power supply. That is why, tomorrow morning I will start the lab on Semiconductor devices dedicated to diodes with my favorite experiment - I will make my students connect a resistor in series to an "ideal" voltage source and then measure the voltage after the resistor with both an "ideal" and real voltmeter.
Then I will suggest to them to close the circuit by another resistor (thus "inventing" the voltage divider)... and finally, by a diode. Then I will ask them why we still need the resistor... and to see why, we may short the resistor:) Fortunately, the power supply is 12V/1A (protected) and the diode is 1N4007.
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