Post History

High Speed Design - Which grounding strategy to choose?

Although I have done multiple PCB designs which passed FCC and CE equivalents using the MCU's/Multiple MCU's, I have a doubt about how to approach the high speed design using FPGA SoC - main thing that bothers me is choosing the right grounding strategy.

By the high-speed design I mean >2GHz memory layout where timings, impedance matching and length matching play the huge role not whether the design would pass the compliance testing but if the design would work at all.

I used to follow the approach similar to Olin's when doing the grounding strategy - https://electronics.stackexchange.com/questions/15135/decoupling-caps-pcb-layout/15143

I am usually putting the good ceramic capacitors very near to the pins of the MCU(mostly in 0603), connect them directly to the pins, join the ground's together(usually in a plane on top or one of the internal layers) and punch the via to the "main ground plane". The use of the power plane is usually avoided since good old 60mil trace is enough for low power devices.

This approach suit me fine even with multiple USB 2.0 Hubs, radio circuitry and dc-dc converters on PCB.

However when doing the DDR4-2666MHz memory layout the return path from the "punch to the nearest GND plane" via and the signal pad will influence the return path impedance of the signal.

Furthermore, FPGA board would be made as a SoM board attached with the carrier/motherboard. SoM board would then be connected with the carrier board "in one single place" - the connector. This leaves the i/o cables connected with the carrier board, which could be made by using the same layout approach as a regular "MCU board" minimizing the patch antenna influence.

Which approach would you follow?