ESD USB Shield Connection & Filtering
I have a handheld ARM Cortex M based device, which has a USB input port.
The product is battery powered and there is no metal chassis.
We are going through CE testing, and are having ESD issues at 4kV contact to the USB shield with reproducibility under IEC 61000-4-2.
On the data lines of the USB port, we have TVS diodes that are working and shunt the ESD to PCB GND plane and the Cortex can keep functioning. When we air discharge at 8kV to the USB port, that TVS diode is working and the unit keeps functioning.
However, when we ESD shock the shield of the USB connector 4kV Contact Discharge (as per the standard), we appear to have some kind of ground bounce that can lock-up the unit.
Because the shield is tied to PCB GND and we don't have a metal chassis, what kind of filtering could we to the shield traces to PCB GND on an updated PCB revision which could help?
Would an RC filter (series R, parallel C) on each shield trace work? I'm trying to think of a filter that would dissapte the ESD to some extent before it hits the PCB GND Plane.
The PCB is tightly populated and 6 layers, so there isn't a whole lot of room for like a discrete PCB GND moat.
It's kind of surprising that the TVS diodes dumping ESD into the GND plane don't affect the microcontroller; however, if the shield dumps ESD into the GND plane it has a very strong effect.
4 answers
A few months ago, I too was looking for answers on how to connect the USB shield with ESD in mind.
I always connect the shield through a resistor to ground and a capacitor to ground (100kΩ and 0.01uF). Pulsing ESD into the shield is a part of the test. The ESD will appear across the capacitor, so it has to absorb the ESD pulse and survive. Can a reasonably sized ceramic capacitor survive? This article: Ceramic capacitors for ESD Protection in Automotive Applications (Vishay, 2020) mentions that an automotive grade ceramic capacitor 0.01uF, rated for 200V, in 0805 package can survive ESD pulses. The article details to what level per IEC 61000-4-2.
Because the shield is tied to PCB GND, [...]
Is your USB shield tied directly to PCB ground? The shield shouldn't be connected directly to ground on the device side. The shield should be directly connected on one end (either end). The other end should be floating, or AC-coupled to GND, but not directly connected to GND. A typical USB host (laptop, hub, wall wart charger) has the direct connection between shield and its ground[1]. Thus, the host end is that one end where the shield is directly connected.
edit: Article by Murata - ESD survivability of capacitors.
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Such design choice is forced on us device designers. We aren't in control of the host hardware. ↩︎
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Connect the shield directly to ground plane
Most manufacturers recommend connecting the USB connector case (which is connected to the cable shield) directly to the PCB ground plane. In theory, when lots of electrons hit the ground plane of an isolated PCB, suddenly changing its voltage relative to planet Earth by thousands of volts, everything on that board should be raised or lowered the same amount (through deliberate bypass capacitors or through unintentional parasitic capacitance). Perhaps some other thing on that board is not isolated -- rather than putting more stuff between the shield and the rest of the board, perhaps you could find that other thing and add ferrite beads or resistors to increase its isolation from planet Earth or add capacitors to the GND plane to reduce its isolation from PCB GND or both.
William D. Kimmel and Daryl D. Gerke say ground the USB shield at both ends, ideally with the connector shell grounded to the enclosure around its entire perimeter. They say the common advice to ground the shield at only one end of the cable (single-point ground) only applies when the path length is short relative to a wavelength (1/20 wavelength), such as audio signals. USB has high-frequency signals that need the shield to be grounded at both ends. "EMI and USB"
Intel says to connect the shield (connector shell) directly the the ground plane, and optionally use a ferrite bead between the USB GND wire and the ground plane. "Intel EMI Design Guidelines for USB Components" p. 9
Silicon Labs says to connect both the USB shield and USB GND directly to PCB ground for both USB self-powered devices and USB bus powered devices "AN0046: USB Hardware Design Guidelines" p. 5 and p. 6
"Atmel AT85C51SND3Bx High Speed USB Design Guidelines" p. 7 and "Atmel AVR32787: AVR32 AT32UC3A3 High Speed USB Design Guidelines" p. 5 doesn't mention the shield or the shell, but the example layouts (such as the one on p. 4) clearly show a wide trace connection between the GND wire (pin 5) and the shell, with lots of vias connecting that GND trace to the GND plane.
I've seen one design guide that contradicts the above advice:
Atmel AVR1017: XMEGA - USB Hardware Design Recommendations p. 7 and 8 recommends putting ESD suppressors between the data lines and the VBus and USB shield (none of the ESD suppressors connected to the GND wire or PCB GND plane), connecting the GND wire to the PCB GND plane, and putting an RC filter between the PCB GND plane and the USB shield (It recommends an RC filter of R = 1 MegaOhm, C = 4.7 nanoFarad).
Another manufacturer suggests keeping your options open:
FTDI says to place a zero-ohm resistor between USB shield and PCB signal ground, which can later be replaced by a capacitor if necessary. "AN_146: USB Hardware Design Guidelines for FTDI ICs" p. 14
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Your question is impossible to answer without carefully looking at the layout and schematic.
However, from gut feel and experience, this smells like poor grounding design. Common mistakes:
- Not a single board-wide master ground plane.
- Too many large islands in the ground plane. The metric of how broken up a ground plane is, is the longest dimension of any hole, not the number of holes. Lots of little holes with ground plane flowing around them is better than the same area in a single hole. That's even worse if that large hole is long and thin (large maximum dimension relative to its area).
- Bypass caps not right up against the power and ground pins they are connected to.
- The ground return of a bypass cap running across the master ground plane instead of locally connecting to the ground pin of the part it is bypassing. Bypass caps shunt high frequency currents generated by the chip they are bypassing. If you run that current across the ground plane, you don't have a ground plane anymore but a center-fed patch antenna.
Maybe you don't care about the small amount of extra radiation, but antennas always work both ways. A better antenna also makes the circuit more susceptible to incoming radiation, like that broad band EMP of a static discharge.
- Sensitive or high-impedance traces not properly handled. A good example is the reset line of a CMOS microcontroller. One little glitch can really ruin your day. You want to make sure that the line is held solidly high during normal operation. This means a decent pullup, possibly with a small cap to ground. If the line has to run across the board, like possibly to a programming header, then consider what it runs next to and what cross-talk it might pick up. In noise situations, a little filtering close to the micro might be in order. That might interfere with programming though. You have to look at this issue carefully.
Curious that you mention bypass caps in the context of ESD, since a discharge is a extreme spike event, unlike the average EMI. To what extent do they help against ESD, aren't they generally far too slow, compared to TVS diodes etc?
Proper bypass capacitors are fast. Their impedance at high frequency is more important than their bulk storage properties. This is why relatively small values like 100 nF work well for bypassing, although they would be useless as bulk capacitance back at the supply, even though that would put them between the exact same two nets.
In the frequency domain, chips look like high frequency current sources between their power and ground pins. The purpose of a bypass cap is to shunt that current to keep it local and the loop small. When done right with proper layout (see #4 above), this keeps the high frequency currents off the much larger loop from the power supply, thru the chip, and back.
I once specified a particular model of 100 pF cap for bypassing a RF chip. After digging thru a bunch of ceramic capacitor datasheets, I found this cap to have lower impedance at the RF frequency than others, even though most of those others had significantly higher capacitance.
All real-world capacitors stop acting like capacitors above some frequency. Since bypass caps deal with high frequencies, they need to still work like capacitors at those frequencies. In our real world with real engineering tradeoffs, that usually means small ceramic caps up to 1 µF, and often lower. The 100 µF to multiple mF caps on the power supply are to store significant energy. They would be useless, however, for bypassing.
Take a look at a datasheet for a 100 µF electrolytic and a 1 µF ceramic. Compare the impedance versus frequency graphs. The 100 µF starts out with 100 times lower impedance, but quickly hits its minimum point with the impedance going back up after that. Note that the 1 µF ceramic keeps going lower in impedance, inversely proportional to the frequency over a much wider frequency range. The result is that the 1 µF has lower impedance to those frequencies that a bypass capacitor needs to address.
Your no 4 is fascinating. So, do you say that the cap should be connected to the ground pin of the part, and this later not connected to the the master ground, or do you say that the cap should be connected very close to the ground pin of the part, while this later may be connected to the master ground.
The latter. The chip still needs to be connected to ground solidly.
The bypass cap also needs to be connected solidly between the chip's power and ground pins. The point I was making is that the current thru the bypass cap should not run across the ground plane. Keep the nasty high frequency currents local and with a small loop area.
A good way to achieve this is to place and route the bypass cap connections with as short and straight traces as reasonably possible. Then put a via close to the ground pin so that the pin is connected to the board-wide ground. Since this via is a single-point connection, the loop current thru the chip and the bypass cap don't flow thru the via. The via is for the lower frequency power supply return current (after the bypass cap has shunted the high frequency current), and the general return currents from signals and the like.
It's kind of surprising that the TVS diodes dumping ESD into the GND plane don't affect the microcontroller; however, if the shield dumps ESD into the GND plane it has a very strong effect.
That's what makes me think that the answer of Nick Alexeev is very relevant: the TVS diode has a small capacitance, and apparently, this capacitance absorbs much of the ESD shock, like the RC combination in Nick Alexeev answer. It would be interesting to try improving this RC combination by the following:
Note: the RC network in Nick Alexeev's answer recalls me the so called "RC snubber" circuit.
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