Your question is impossible to answer without carefully looking at the layout and schematic.
However, from gut feel and experience, this smells like poor grounding design. Common mistakes:
- Not a single board-wide master ground plane.
- Too many large islands in the ground plane. The metric of how broken up a ground plane is, is the longest dimension of any hole, not the number of holes. Lots of little holes with ground plane flowing around them is better than the same area in a single hole. That's even worse if that large hole is long and thin (large maximum dimension relative to its area).
- Bypass caps not right up against the power and ground pins they are connected to.
- The ground return of a bypass cap running across the master ground plane instead of locally connecting to the ground pin of the part it is bypassing. Bypass caps shunt high frequency currents generated by the chip they are bypassing. If you run that current across the ground plane, you don't have a ground plane anymore but a center-fed patch antenna.
Maybe you don't care about the small amount of extra radiation, but antennas always work both ways. A better antenna also makes the circuit more susceptible to incoming radiation, like that broad band EMP of a static discharge.
- Sensitive or high-impedance traces not properly handled. A good example is the reset line of a CMOS microcontroller. One little glitch can really ruin your day. You want to make sure that the line is held solidly high during normal operation. This means a decent pullup, possibly with a small cap to ground. If the line has to run across the board, like possibly to a programming header, then consider what it runs next to and what cross-talk it might pick up. In noise situations, a little filtering close to the micro might be in order. That might interfere with programming though. You have to look at this issue carefully.
Curious that you mention bypass caps in the context of ESD, since a discharge is a extreme spike event, unlike the average EMI. To what extent do they help against ESD, aren't they generally far too slow, compared to TVS diodes etc?
Proper bypass capacitors are fast. Their impedance at high frequency is more important than their bulk storage properties. This is why relatively small values like 100 nF work well for bypassing, although they would be useless as bulk capacitance back at the supply, even though that would put them between the exact same two nets.
In the frequency domain, chips look like high frequency current sources between their power and ground pins. The purpose of a bypass cap is to shunt that current to keep it local and the loop small. When done right with proper layout (see #4 above), this keeps the high frequency currents off the much larger loop from the power supply, thru the chip, and back.
I once specified a particular model of 100 pF cap for bypassing a RF chip. After digging thru a bunch of ceramic capacitor datasheets, I found this cap to have lower impedance at the RF frequency than others, even though most of those others had significantly higher capacitance.
All real-world capacitors stop acting like capacitors above some frequency. Since bypass caps deal with high frequencies, they need to still work like capacitors at those frequencies. In our real world with real engineering tradeoffs, that usually means small ceramic caps up to 1 µF, and often lower. The 100 µF to multiple mF caps on the power supply are to store significant energy. They would be useless, however, for bypassing.
Take a look at a datasheet for a 100 µF electrolytic and a 1 µF ceramic. Compare the impedance versus frequency graphs. The 100 µF starts out with 100 times lower impedance, but quickly hits its minimum point with the impedance going back up after that. Note that the 1 µF ceramic keeps going lower in impedance, inversely proportional to the frequency over a much wider frequency range. The result is that the 1 µF has lower impedance to those frequencies that a bypass capacitor needs to address.
Your no 4 is fascinating. So, do you say that the cap should be connected to the ground pin of the part, and this later not connected to the the master ground, or do you say that the cap should be connected very close to the ground pin of the part, while this later may be connected to the master ground.
The latter. The chip still needs to be connected to ground solidly.
The bypass cap also needs to be connected solidly between the chip's power and ground pins. The point I was making is that the current thru the bypass cap should not run across the ground plane. Keep the nasty high frequency currents local and with a small loop area.
A good way to achieve this is to place and route the bypass cap connections with as short and straight traces as reasonably possible. Then put a via close to the ground pin so that the pin is connected to the board-wide ground. Since this via is a single-point connection, the loop current thru the chip and the bypass cap don't flow thru the via. The via is for the lower frequency power supply return current (after the bypass cap has shunted the high frequency current), and the general return currents from signals and the like.