Post History

60%

+1 −0

Q&A Is it possible to design an n-bit full adder using SystemVerilog?

I am trying to design a full adder in SystemVerilog. I searched on Wikipedia and I found this https://en.wikibooks.org/w/index.php?title=Microprocessor_Design/Add_and_Subtract_Blocks module full_...

1 answer · posted 3y ago by System‭ · last activity 3y ago by System‭

Question digital-logic-circuit computer-arithmetic systemverilog

#6: Post edited by (deleted user) · 2021-02-23T12:59:31Z (about 3 years ago)

Copy Link

Raw

Markdown

How do I design an n-bit full adder using SystemVerilog?

Is it possible to design an n-bit full adder using SystemVerilog?

#5: Post edited by (deleted user) · 2021-02-23T12:59:00Z (about 3 years ago)

Copy Link

Raw

Markdown

~~How do I design n-bit full adder using SystemVerilog?~~

How do I design an n-bit full adder using SystemVerilog?

#4: Post edited by (deleted user) · 2021-02-23T12:58:46Z (about 3 years ago)

Copy Link

Raw

Markdown

#3: Post edited by (deleted user) · 2021-02-23T12:55:27Z (about 3 years ago)

Copy Link

Raw

Markdown

digital-logic-circuit systemverilog

#2: Post edited by (deleted user) · 2021-02-23T12:52:49Z (about 3 years ago)

Copy Link

Raw

Markdown

~~How to design n-bit full adder in SystemVerilog?~~

How do I design n-bit full adder using SystemVerilog?

#1: Initial revision by (deleted user) · 2021-02-23T12:45:59Z (about 3 years ago)

Copy Link

Raw

Markdown

How to design n-bit full adder in SystemVerilog?

I am trying to design a full adder in SystemVerilog. 

I searched on Wikipedia and I found this https://en.wikibooks.org/w/index.php?title=Microprocessor_Design/Add_and_Subtract_Blocks

```
module full_adder(a, b, cin, cout, s);
   input a, b, cin;
   output cout, s;
   wire temp;
   temp = a ^ b;
   s = temp ^ cin;
   cout = (cin & temp) | (a & b);
endmodule
```

But this code seems quite lengthy, and works for only the 1-bit case. Is there code which is shorter and can work for the n-bit case?

systemverilog

Communities

Post History