Q&A

# Is it possible to design an n-bit full adder using SystemVerilog?

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I am trying to design a full adder in SystemVerilog.

I searched on Wikipedia and I found this https://en.wikibooks.org/w/index.php?title=Microprocessor_Design/Add_and_Subtract_Blocks

module full_adder(a, b, cin, cout, s);
input a, b, cin;
output cout, s;
wire temp;
temp = a ^ b;
s = temp ^ cin;
cout = (cin & temp) | (a & b);
endmodule


But this code seems quite lengthy, and works for only the 1-bit case. Is there code which is shorter and can work for the n-bit case?

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module full_adder
#(parameter WIDTH = 4)
(input logic [WIDTH - 1: 0] a,
b,
input logic carry_in,
output logic carry_out,
output logic [WIDTH - 1: 0] sum);

assign {carry_out, sum} = a + b + carry_in;

endmodule


The above design is parameterised, so full adders of any positive integral widths can be obtained by changing the value of the WIDTH parameter.

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