Is it possible to design an n-bit full adder using SystemVerilog?
I am trying to design a full adder in SystemVerilog.
I searched on Wikipedia and I found this https://en.wikibooks.org/w/index.php?title=Microprocessor_Design/Add_and_Subtract_Blocks
module full_adder(a, b, cin, cout, s); input a, b, cin; output cout, s; wire temp; temp = a ^ b; s = temp ^ cin; cout = (cin & temp) | (a & b); endmodule
But this code seems quite lengthy, and works for only the 1-bit case. Is there code which is shorter and can work for the n-bit case?