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Q&A

How could you model a 10M/100M Ethernet PHY architecture?

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Application notes for microcontrollers or other ICs that have an internal 10M/100M ethernet PHY module differ in their requirements for the external interface components. It seems that the PHY design differs enough between devices such that the external component architecture needs to depend on which product you are using. For curiosity I am interested in creating a simplified SPICE model of the PHY and the external components so that I can learn about how the PHY architecture impacts the external components. For example, I'm interested in understanding the requirement for the center tap of the transformer to be tied to VDD. Does anyone have some advice on modeling the PHY and the external components or insight into the external component architecture requirements?

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I'm not going to get into how to model the PHY interface, but will try to explain why there are differences.

The type of Ethernet you are talking about is transformer-coupled. The line itself is a differential pair with 50 Ω impedance. However, since a transformer is supposed to be between a PHY and the line anyway, manufacturers are free to use different voltage levels and impedances on the PHY side of the transformer, as long as the correct transformer is used such that the line side adheres to the standard.

A center-tapped primary for the PHY side can be useful to reduce the complexity of the driving circuit. This allows tying the center tap to the positive supply, then only needing low-side drivers on each of the ends. That can be convenient when the PHY is operating from a single positive supply. Only one driver is turned on at a time, depending on whether driving the differential line on the secondary of the transformer to the positive or negative state.

PHY designs have largely converged to a few common configurations. Different transformers are available to support these. Look at the offerings from a single company, like Pulse Engineering for example. You will see a number of variations, all serving the same ultimate purpose of driving the kind of Ethernet lines you mention. Many of the variations are about what is available for common mode noise suppression, but some are also for different ratios between the line and PHY sides, and whether center taps are provided. Another source of variation is whether connections are available to support some types of power over Ethernet.


Would you elaborate on how the center tap tied to VDD reduces the driver complexity for a single supply system? I’m having difficulty understanding how the center tap allows for the use of low side drivers.

Here is the basic concept of a center-tapped drive:

This allows for producing a symmetric ± output signal from a circuit running from a single positive supply. Hopefully you can see why it would be convenient for a PHY to run from a single positive supply.

At most one of the two transistors is turned on at a time. Turning on Q1 results in an output pulse (from the transformer secondary) of one polarity, and turning on Q2 results in the same magnitude pulse but with opposite polarity. This is a convenient topology that fits well with the requirements of an integrated circuit. Note that the inputs to both switcher are ground-referenced.

Without the center tap, both ends of the primary would need to be driven high and low. Something like an H bridge would generally be needed. This center tap drive circuit is rather simpler.

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