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How could you model a 10M/100M Ethernet PHY architecture?

Application notes for microcontrollers or other ICs that have an internal 10M/100M ethernet PHY module differ in their requirements for the external interface components.  It seems that the PHY design differs enough between devices such that the external component architecture needs to depend on which product you are using.  For curiosity I am interested in creating a simplified SPICE model of the PHY and the external components so that I can learn about how the PHY architecture impacts the external components.  For example, I'm interested in understanding the requirement for the center tap of the transformer to be tied to VDD.  Does anyone have some advice on modeling the PHY and the external components or insight into the external component architecture requirements?