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Q&A

SPI modes difference

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What is a difference between SPI stream and memory mapped SPI?

PS SPI is a peripheral.

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2 comment threads

Isn't *"SPI is a peripheral"* misleading? Isn't it the ***interface specification*** [Serial Periphe... (1 comment)
Frank, could you please add a link to the text where you saw these terms? Otherwise, if would be too... (2 comments)

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"Stream" and "memory mapped" should be defined in the documentation for whatever microcontroller you are using.

"Memory mapped" can mean different things. It might be just a different way of saying DMA, meaning the peripheral gets and puts data directly to memory buffers without code intervention. Another completely different meaning is that external I/O sources and destinations appear in the memory space, as opposed to there being a separate I/O space. Memory mapping versus an I/O space are two different ways of giving code access to particular addresses on external busses.

"Stream" can also mean many things. When used in opposition to "memory mapped", I can only guess that it means something like programmed I/O as opposed to DMA.

Again, the only real answer is in the datasheet for your particular microcontroller.

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I am studying DMA blocks in VIVADo which I can use as a "connector" between SPI slave/master and CPU.... (1 comment)
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From the point of view of the SPI peripheral (and any debugging tools you have directly connected to the SPI bus), there is no difference between SPI stream and memory-mapped SPI. The difference is entirely in how the data going to and coming from the SPI bus is translated to the rest of the system.

SPI in a typical processor

Many families of 8-bit peripheral ICs have a USART IC or a serial communication controller IC (SCC IC) that supports SPI. The USART (in SPI mode) has 2 different interfaces: the SPI interface that is wired to SPI peripheral(s) with the 4-wire SPI bus, and a system bus interface wired to the CPU. (Typically the USART system bus interface has an 8-bit data bus and a few other control lines, such as a chip select wire coming from a 74HC138 address decoder chip).

More recently, many microcontrollers have integrated that USART functionality into the same chip as a CPU (an "on-chip peripheral").

Some CPUs have special machine-language instructions for reading and writing to such peripherals ("port-mapped IO" PMIO), and some computers have the USART wired to the CPU such that it only responds to such instructions. The USART in those computers is wired to ignore normal memory reads and writes.

Many computers have the USART wired to the CPU in such a way that the USART respond to the same common machine-language instructions that are used to read and write to RAM ("memory-mapped IO" MMIO), at some specific memory address. (This is by far the most common meaning of "memory-mapped SPI", although your specific case seems to be different).

Some systems support DMA streaming through the system bus, where DMA hardware reads from one block of RAM to stream out the SPI bus while simultaneously writing data, streaming in from the SPI bus, to a different block of RAM, while the CPU can be doing other jobs.

FPGA configuration memory SPI

Many systems that have a FPGA chip also have a "FPGA configuration memory" chip next to it. On power-up, the FPGA loads the design bitstream from the configuration memory. Typically the interface between the FPGA and the external memory chip is a SPI bus.

the AXI Quad SPI IP core

If I'm reading correctly page 9 and 10 of "AXI Quad SPI: LogiCORE IP Product Guide: Vivado Design Suite" (Xilinx 2021), the "AXI Quad SPI IP core" generated by Vivado for FPGAs has 4 different interfaces:

  • SPI bus interface #1, same as any other SPI interface
  • SPI bus interface #2, same as any other SPI interface (2 SPI buses allows independently reading and writing to 2 different SPI peripherals at the same time, which is convenient when one or both of them are slow). (I suspect that neither of these SPI buses can be used for configuration memory).
  • AXI4 Lite interface
  • AXI4 memory-mapped interface

Both of the AXI4 interfaces are connected to the same AXI4 bus, which is used as a system bus. Presumably also connected to that bus is a soft microprocessor IP core, such as a MicroBlaze IP core, inside the same FPGA chip as the AXI Quad SPI IP core.

The AXI4 Lite interface acts much like the system bus interface of a typical USART. Some program on the processor uses some sort of read and write instructions to registers inside the AXI Quad SPI IP core, including the most recent complete byte coming from the SPI bus and the next byte to send out the SPI bus. It appears that this can also be set up to do a DMA SPI stream.

The AXI4 memory-mapped interface is very different from most SPI interfaces. This AXI Quad SPI IP core "memory mapped SPI" is used for XIP (execute in place). The CPU, as normal, sends the PC (the address of the next instruction) out the address bus (this happens with every instruction, not just "port I/O" instructions or "load/store data" instructions). If that address matches the AXI Quad SPI memory-mapped interface address, the AXI Quad SPI IP core sends a "READ" instruction including those address bits out to some SPI memory device, reads the data back from that memory device, and sends that instruction back on the AXI4 data bus to the CPU core to execute, emulating a parallel memory device.

p.s.: You would have gotten an answer much sooner if you had posted a direct link (URL, starting with "http") of the document that where you read those phrases.

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