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Q&A What is the role of master clock speed on DAC

In protocol I2S we have 3 signal + one none standard master clock(Mentioined by Olin Lathrop): 1.data 2.lrck/fck (frame synchronizer) 3.bck (bit clock) 4.mck/sck (master clock) Question 1: Why we...

2 answers  ·  posted 1y ago by mohammadsdtmnd‭  ·  last activity 1y ago by mohammadsdtmnd‭

Question clock audio DAC
#5: Post edited by user avatar mohammadsdtmnd‭ · 2023-04-10T05:58:34Z (over 1 year ago)
extending question
  • In protocol I2S we have 3 signal + one none standard master clock(Mentioined by Olin Lathrop):
  • 1.data 2.lrck/fck (frame synchronizer) 3.bck (bit clock) 4.mck/sck (master clock)
  • Question 1: Why we need master clock? I think simply some devices need clock to work, this master clock can provide clock for them to work.
  • Question 2: In DAC IC PCM5102a we have specification about relation of master clock (sck) related to sampling frequency (lrck):
  • ![sck vs lrck](https://electrical.codidact.com/uploads/jvix0ran3i8gc6xp2d7yiez5d5i5)
  • But what is the difference between these multiplier? In other word by providing higher or lower frequency clock for DAC what will change, what will happens? And how we can chose any of them? I can't find anything about it on it's [datasheet](https://www.ti.com/lit/ds/symlink/pcm5102a.pdf?ts=1680037818805&ref_url=https%253A%252F%252Fwww.ti.com%252Fproduct%252FPCM5102A).
  • Question 3: As you can see on the picture from datasheet appended above, whithout providing sck, it will uses it's own pll to generate clock for itself but according to picture we have two speed supported 128x and 192x. which one will be selected how, again I couldn't find anything on datasheet.
  • In protocol I2S we have 3 signal + one none standard master clock(Mentioined by Olin Lathrop):
  • 1.data 2.lrck/fck (frame synchronizer) 3.bck (bit clock) 4.mck/sck (master clock)
  • Question 1: Why we need master clock? I think simply some devices need clock to work, this master clock can provide clock for them to work.
  • Question 2: In DAC IC PCM5102a we have specification about relation of master clock (sck) related to sampling frequency (lrck):
  • ![sck vs lrck](https://electrical.codidact.com/uploads/jvix0ran3i8gc6xp2d7yiez5d5i5)
  • But what is the difference between these multiplier? In other word by providing higher or lower frequency clock for DAC what will change, what will happens? And how we can chose any of them? I can't find anything about it on it's [datasheet](https://www.ti.com/lit/ds/symlink/pcm5102a.pdf?ts=1680037818805&ref_url=https%253A%252F%252Fwww.ti.com%252Fproduct%252FPCM5102A).
  • Question 3: As you can see on the picture from datasheet appended above, whithout providing sck, it will uses it's own pll to generate clock for itself but according to picture we have two speed supported 128x and 192x. which one will be selected how, again I couldn't find anything on datasheet.
  • Question 4: Also the datasheet mentioned 1x/2x/4x/8x interpolatino is availible, but there isn't way to setting it, does it relate to MCK?How?
#4: Post edited by user avatar mohammadsdtmnd‭ · 2023-04-04T04:04:37Z (over 1 year ago)
  • In protocol I2S we have 3 signal + one none standard master clock(Mentioined by Olin latrop):
  • 1.data 2.lrck/fck (frame synchronizer) 3.bck (bit clock) 4.mck/sck (master clock)
  • Question 1: Why we need master clock? I think simply some devices need clock to work, this master clock can provide clock for them to work.
  • Question 2: In DAC IC PCM5102a we have specification about relation of master clock (sck) related to sampling frequency (lrck):
  • ![sck vs lrck](https://electrical.codidact.com/uploads/jvix0ran3i8gc6xp2d7yiez5d5i5)
  • But what is the difference between these multiplier? In other word by providing higher or lower frequency clock for DAC what will change, what will happens? And how we can chose any of them? I can't find anything about it on it's [datasheet](https://www.ti.com/lit/ds/symlink/pcm5102a.pdf?ts=1680037818805&ref_url=https%253A%252F%252Fwww.ti.com%252Fproduct%252FPCM5102A).
  • Question 3: As you can see on the picture from datasheet appended above, whithout providing sck, it will uses it's own pll to generate clock for itself but according to picture we have two speed supported 128x and 192x. which one will be selected how, again I couldn't find anything on datasheet.
  • In protocol I2S we have 3 signal + one none standard master clock(Mentioined by Olin Lathrop):
  • 1.data 2.lrck/fck (frame synchronizer) 3.bck (bit clock) 4.mck/sck (master clock)
  • Question 1: Why we need master clock? I think simply some devices need clock to work, this master clock can provide clock for them to work.
  • Question 2: In DAC IC PCM5102a we have specification about relation of master clock (sck) related to sampling frequency (lrck):
  • ![sck vs lrck](https://electrical.codidact.com/uploads/jvix0ran3i8gc6xp2d7yiez5d5i5)
  • But what is the difference between these multiplier? In other word by providing higher or lower frequency clock for DAC what will change, what will happens? And how we can chose any of them? I can't find anything about it on it's [datasheet](https://www.ti.com/lit/ds/symlink/pcm5102a.pdf?ts=1680037818805&ref_url=https%253A%252F%252Fwww.ti.com%252Fproduct%252FPCM5102A).
  • Question 3: As you can see on the picture from datasheet appended above, whithout providing sck, it will uses it's own pll to generate clock for itself but according to picture we have two speed supported 128x and 192x. which one will be selected how, again I couldn't find anything on datasheet.
#3: Post edited by user avatar mohammadsdtmnd‭ · 2023-04-04T04:04:11Z (over 1 year ago)
  • In protocol I2S we have 4 signal:
  • 1.data 2.lrck/fck (frame synchronizer) 3.bck (bit clock) 4.mck/sck (master clock)
  • Question 1: Why we need master clock? I think simply some devices need clock to work, this master clock can provide clock for them to work.
  • Question 2: In DAC IC PCM5102a we have specification about relation of master clock (sck) related to sampling frequency (lrck):
  • ![sck vs lrck](https://electrical.codidact.com/uploads/jvix0ran3i8gc6xp2d7yiez5d5i5)
  • But what is the difference between these multiplier? In other word by providing higher or lower frequency clock for DAC what will change, what will happens? And how we can chose any of them? I can't find anything about it on it's [datasheet](https://www.ti.com/lit/ds/symlink/pcm5102a.pdf?ts=1680037818805&ref_url=https%253A%252F%252Fwww.ti.com%252Fproduct%252FPCM5102A).
  • Question 3: As you can see on the picture from datasheet appended above, whithout providing sck, it will uses it's own pll to generate clock for itself but according to picture we have two speed supported 128x and 192x. which one will be selected how, again I couldn't find anything on datasheet.
  • In protocol I2S we have 3 signal + one none standard master clock(Mentioined by Olin latrop):
  • 1.data 2.lrck/fck (frame synchronizer) 3.bck (bit clock) 4.mck/sck (master clock)
  • Question 1: Why we need master clock? I think simply some devices need clock to work, this master clock can provide clock for them to work.
  • Question 2: In DAC IC PCM5102a we have specification about relation of master clock (sck) related to sampling frequency (lrck):
  • ![sck vs lrck](https://electrical.codidact.com/uploads/jvix0ran3i8gc6xp2d7yiez5d5i5)
  • But what is the difference between these multiplier? In other word by providing higher or lower frequency clock for DAC what will change, what will happens? And how we can chose any of them? I can't find anything about it on it's [datasheet](https://www.ti.com/lit/ds/symlink/pcm5102a.pdf?ts=1680037818805&ref_url=https%253A%252F%252Fwww.ti.com%252Fproduct%252FPCM5102A).
  • Question 3: As you can see on the picture from datasheet appended above, whithout providing sck, it will uses it's own pll to generate clock for itself but according to picture we have two speed supported 128x and 192x. which one will be selected how, again I couldn't find anything on datasheet.
#2: Post edited by user avatar mohammadsdtmnd‭ · 2023-03-29T07:58:55Z (over 1 year ago)
  • In protocol I2S we have 4 signal:
  • 1.data 2.lrck/fck (frame synchronizer) 3.bck (bit clock) 4.mck/sck (master clock)
  • Question 1: Why we need master clock? I think simply some devices need clock to work, this master clock can provide clock for them to work.
  • Question 2: In DAC IC PCM5102a we have specification about relation of master clock (sck) related to sampling frequency (lrck):
  • ![sck vs lrck](https://electrical.codidact.com/uploads/jvix0ran3i8gc6xp2d7yiez5d5i5)
  • But what is the difference between these multiplier? In other word by providing higher or lower frequency clock for DAC what will change, what will happens? And how we can chose any of them? I can't find anything about it on it's [datasheet](https://www.ti.com/lit/ds/symlink/pcm5102a.pdf?ts=1680037818805&ref_url=https%253A%252F%252Fwww.ti.com%252Fproduct%252FPCM5102A).
  • Question 3: As you can see on the picture from datasheet appended above, whithout providing sck, it will uses it's own pll to generate clock for itself but according to picture we have two speed supported 128x and 192x. which one will be selected how, gaind I couldn't find anything on datasheet.
  • In protocol I2S we have 4 signal:
  • 1.data 2.lrck/fck (frame synchronizer) 3.bck (bit clock) 4.mck/sck (master clock)
  • Question 1: Why we need master clock? I think simply some devices need clock to work, this master clock can provide clock for them to work.
  • Question 2: In DAC IC PCM5102a we have specification about relation of master clock (sck) related to sampling frequency (lrck):
  • ![sck vs lrck](https://electrical.codidact.com/uploads/jvix0ran3i8gc6xp2d7yiez5d5i5)
  • But what is the difference between these multiplier? In other word by providing higher or lower frequency clock for DAC what will change, what will happens? And how we can chose any of them? I can't find anything about it on it's [datasheet](https://www.ti.com/lit/ds/symlink/pcm5102a.pdf?ts=1680037818805&ref_url=https%253A%252F%252Fwww.ti.com%252Fproduct%252FPCM5102A).
  • Question 3: As you can see on the picture from datasheet appended above, whithout providing sck, it will uses it's own pll to generate clock for itself but according to picture we have two speed supported 128x and 192x. which one will be selected how, again I couldn't find anything on datasheet.
#1: Initial revision by user avatar mohammadsdtmnd‭ · 2023-03-29T07:56:32Z (over 1 year ago) 
What is the role of master clock speed on DAC
In protocol I2S we have 4 signal:
1.data 2.lrck/fck (frame synchronizer) 3.bck (bit clock) 4.mck/sck (master clock)

Question 1: Why we need master clock? I think simply some devices need clock to work, this master clock can provide clock for them to work.

Question 2: In DAC IC PCM5102a we have specification about relation of master clock (sck) related to sampling frequency (lrck):
![sck vs lrck](https://electrical.codidact.com/uploads/jvix0ran3i8gc6xp2d7yiez5d5i5)
But what is the difference between these multiplier? In other word by providing higher or lower frequency clock for DAC what will change, what will happens? And how we can chose any of them? I can't find anything about it on it's [datasheet](https://www.ti.com/lit/ds/symlink/pcm5102a.pdf?ts=1680037818805&ref_url=https%253A%252F%252Fwww.ti.com%252Fproduct%252FPCM5102A).


Question 3: As you can see on the picture from datasheet appended above, whithout providing sck, it will uses it's own pll to generate clock for itself but according to picture we have two speed supported 128x and 192x. which one will be selected how, gaind I couldn't find anything on datasheet.
clock audio DAC