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What effect does an oscillator potentially have on a SPI clk signal if the oscillator is on the top layer, with GND and VCC layer in between on a four layer board. I know running it on the same lay...
#1: Initial revision
by
Hawk2020
·
2023-12-01T16:07:53Z (5 months ago)
Noise from oscillator on top layer to clock on bottom layer with VCC & GND layers between
What effect does an oscillator potentially have on a SPI clk signal if the oscillator is on the top layer, with GND and VCC layer in between on a four layer board. I know running it on the same layer within a certain distance will have coupling effects that could cause noise and the 3W rule. I don't see people talking about different layers as much though. The clock is on the bottom like in the picture below. I know speed of oscillator and clock will likely determine if it will actually cause issues, but I am wondering about the general physics/practical noise that could be caused. 