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As of the early 2020s, common technology nodes for SSI (Small-Scale Integration) and MSI (Medium-Scale Integration) ICs include nodes such as 180nm, 130nm, 90nm, 65nm, 45nm, and 28nm. Each technolo...
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#2: Post edited
by
TonyStewart
·
2023-12-02T14:35:49Z (5 months ago)
- As of the early 2020s, common technology nodes for SSI (Small-Scale Integration) and MSI (Medium-Scale Integration) ICs include nodes such as 180nm, 130nm, 90nm, 65nm, 45nm, and 28nm. Each technology node represents a specific level of lithographic resolution that costs billions to create.
- Migrating a product to a new process also has a cost of conversion and validation. Specifications for latency, risetime, power dissipation would be impacted and no longer be valid second sources, if a faster part caused a race condition. So all OEMs who make the same parts conform to the same specifications for the most part. Backwards compatibility is often more important than speeding up an old technology. That is why there are so many CMOS families now.
However, they have standardized on Rdson=Vol/Io for a given Vdd max range like 5.5 or 3.6 to 1.2 as the crossover currents and dynamic power dissipation are practical goals with each major lithographic reduction, while meeting the same noise error margins and high yields are other requirements. 2nm wafers are in prototype now while development on 1nm lithography is being worked on by a friend of mine, but it's real hard.
- As of the early 2020s, common technology nodes for SSI (Small-Scale Integration) and MSI (Medium-Scale Integration) ICs include nodes such as 180nm, 130nm, 90nm, 65nm, 45nm, and 28nm. Each technology node represents a specific level of lithographic resolution that costs billions to create.
- Migrating a product to a new process also has a cost of conversion and validation. Specifications for latency, risetime, power dissipation would be impacted and no longer be valid second sources, if a faster part caused a race condition. So all OEMs who make the same parts conform to the same specifications for the most part. Backwards compatibility is often more important than speeding up an old technology. That is why there are so many CMOS families now.
- However, they have standardized on Rdson=Vol/Io for a given Vdd max range like 5.5 or 3.6 to 1.2 as the crossover currents and dynamic power dissipation are practical goals with each major lithographic reduction, while meeting noise error margins and high yields and other requirements. 2nm wafers are in prototype now while development on 1nm lithography is being worked on by a friend of mine, but it's real hard.
#1: Initial revision
by
TonyStewart
·
2023-12-02T14:25:37Z (5 months ago)
As of the early 2020s, common technology nodes for SSI (Small-Scale Integration) and MSI (Medium-Scale Integration) ICs include nodes such as 180nm, 130nm, 90nm, 65nm, 45nm, and 28nm. Each technology node represents a specific level of lithographic resolution that costs billions to create. Migrating a product to a new process also has a cost of conversion and validation. Specifications for latency, risetime, power dissipation would be impacted and no longer be valid second sources, if a faster part caused a race condition. So all OEMs who make the same parts conform to the same specifications for the most part. Backwards compatibility is often more important than speeding up an old technology. That is why there are so many CMOS families now. However, they have standardized on Rdson=Vol/Io for a given Vdd max range like 5.5 or 3.6 to 1.2 as the crossover currents and dynamic power dissipation are practical goals with each major lithographic reduction, while meeting the same noise error margins and high yields are other requirements. 2nm wafers are in prototype now while development on 1nm lithography is being worked on by a friend of mine, but it's real hard.