What fabrication process is being used for jellybean parts
I want to know why the top-of-the-line CPUs and GPUs from Intel, NVIDIA, and AMD are all bragging about the fabrication process (7nm and 5nm) and trying to be consistently smaller. At the same time, on the other side of the industry, the everyday utility ICs like power management ICs, boos or buck converters, etc, never mention which fabrication process are they using?
Let's take some relative Ti and AD chips as examples: https://www.ti.com/product/TPS610333 https://www.analog.com/en/products/ltc7880.html
Is it possible to find out what fabrication process, wafer size, etc these jellybean parts are made of? Is it at all important? Is it even possible or makes sense to make such chips in cutting-edge 4nm and 5nm processes?
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As of the early 2020s, common technology nodes for SSI (Small-Scale Integration) and MSI (Medium-Scale Integration) ICs include nodes such as 180nm, 130nm, 90nm, 65nm, 45nm, and 28nm. Each technology node represents a specific level of lithographic resolution that costs billions to create. Migrating a product to a new process also has a cost of conversion and validation. Specifications for latency, risetime, power dissipation would be impacted and no longer be valid second sources, if a faster part caused a race condition. So all OEMs who make the same parts conform to the same specifications for the most part. Backwards compatibility is often more important than speeding up an old technology. That is why there are so many CMOS families now.
However, they have standardized on Rdson=Vol/Io for a given Vdd max range like 5.5 or 3.6 to 1.2 as the crossover currents and dynamic power dissipation are practical goals with each major lithographic reduction, while meeting noise error margins and high yields and other requirements. 2nm wafers are in prototype now while development on 1nm lithography is being worked on by a friend of mine, but it's real hard.
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[I used to work at Microchip.]
Is it [node size] at all important [for power management ICs] ?
For power conversion ICs cutting edge MOSFETs on the scale of 5nm aren't important, because power MOSFETs are large. Larger scale MOSFETs (older generation processes) are cheaper than the cutting edge. So, it doesn't make a lot of sense to push the scale when that doesn't give an edge.
Is it even possible or makes sense to make such chips [power management ICs] in cutting-edge 4nm and 5nm processes?
Yes, it should be possible. But would that give you an edge?
If DSP is required for power conversion, then it would probably be done with a chipset where DSP and power stage are made with different processes.
Is it possible to find out what fabrication process, wafer size, etc these jellybean parts are made of?
You're asking for insider information. For any given jellybean its fabrication process, wafer size, name of the contract fab is proprietary information of the given manufacturer. The closest you can get to that information from the outside is by looking at capabilities of contract semiconductor fabs; you may glean some coarse aggregate picture. Usually the details of the contract fab capabilities are behind an NDA too.
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The following users marked this post as Works for me:
| User | Comment | Date |
|---|---|---|
| dekker | (no comment) | Dec 17, 2023 at 22:11 |
I want to know why the top-of-the-line CPUs and GPUs from Intel, NVIDIA, and AMD are all bragging about the fabrication process (7nm and 5nm) and trying to be consistently smaller.
It's marketing hype intended to make them look more high tech than the other guy. There is little reason the end user should care about the minimum feature size of the process.
There are reasons for making the features smaller. Smaller features means more transistors fit in the same area. That means the same chip is smaller, uses less of the wafer, and has a smaller chance of hitting a defect in this wafer. Smaller features can also allow lower power dissipation.
There are also drawbacks to smaller transistors. The difference between the on-state and off-state gets smaller. That together with decreased voltage bumps into limits of high on-state resistance slowing edges, and low off-state resistance causing leakage. The leakage of a single transistor is tiny, but with literally millions of them on a chip, it adds up. That leakage times the power supply voltage is power that is always dissipated. Now consider that cramming more transistors that leak more into the same area increases the power density. Pretty soon you approach power densities of common soldering iron tips. No, seriously.
Again, though, none of this matters to the end consumer. They should only care about specs like speed, power requirements, cooling requirements, and price. What technobabble was used under the hood to achieve them is mostly irrelevant.
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