Communities

Writing
Writing
Codidact Meta
Codidact Meta
The Great Outdoors
The Great Outdoors
Photography & Video
Photography & Video
Scientific Speculation
Scientific Speculation
Cooking
Cooking
Electrical Engineering
Electrical Engineering
Judaism
Judaism
Languages & Linguistics
Languages & Linguistics
Software Development
Software Development
Mathematics
Mathematics
Christianity
Christianity
Code Golf
Code Golf
Music
Music
Physics
Physics
Linux Systems
Linux Systems
Power Users
Power Users
Tabletop RPGs
Tabletop RPGs
Community Proposals
Community Proposals
tag:snake search within a tag
answers:0 unanswered questions
user:xxxx search by author id
score:0.5 posts with 0.5+ score
"snake oil" exact phrase
votes:4 posts with 4+ votes
created:<1w created < 1 week ago
post_type:xxxx type of post
Search help
Notifications
Mark all as read See all your notifications »
Q&A

Are LDOs more efficient than switching regulators in very low currents?

+2
−0

I'm looking for a power supply to power up the VCORE of an mcu.
The chip is an STM32 microcontroller (LQFP) and the maximum current it will draw is no more than 150mA.

The input will be 3V-5V max and the output 1.2V

I usually go with LDO even for the whole chip power but in this case I need something very efficient to extend the battery life as much as possible.

History
Why does this post require attention from curators or moderators?
You might want to add some details to your flag.
Why should this post be closed?

1 comment thread

Title doesn't match question. (1 comment)

3 answers

+5
−0

The efficiency of the LDO is a function of the input and output voltages.

$$\eta = \frac {P_{out}} {P_{in}} = \frac {I_{out} V_{out}} {I_{in} V_{in}}$$

$I_{out} \approx I_{in}$ for a series linear regulator ¹ ². Input and output currents cancel.

$$\eta \approx \frac {V_{out}} {V_{in}}$$

In your case where Vout is 1.2V, Vin is between 3V and 5V, the efficiency of the LDO will be between 40% and 24%. Any half-decent buck converter would have at least 80% efficiency at the expense of parts cost, switching noise, PCB real estate, engineering risk. An LDO with low efficiency can still be used when current is insignificant. Threshold of insignificance is decided individually for each end product.

¹ LDO's own quiescent current becomes significant when calculating standby current consumption. On the scale of 100mA current draw the LDO's quiescent current is insignificant.

² Series regulators, as opposed to the less common shunt regulators.

History
Why does this post require attention from curators or moderators?
You might want to add some details to your flag.

0 comment threads

+4
−0

Do the math.

At 5 V in and 1.2 V out, a linear regulator is limited to (1.2 V)/(5.0 V) = 24% efficiency. At 3 V in, the limit is 40%. The actual efficiency will be little less due to the current that the regulator itself uses to operate, but compared to 150 mA that will be negligible with pretty much any modern regulator.

So, the question becomes can a switcher do better than 40% efficiency in going from 5 V to 1.2 V? Absolutely. I'd expect to find switchers that can do 80% or better with 3 to 5 V in and 1.2 V out at 150 mA.

At these low voltages, you definitely need synchronous rectification to achieve good efficiency, but that will be built into any competent chip aimed at this kind of operating point. At 150 mA, you should be able to find a chip with the switching element built-in, which also helps with synchronous rectification. You will need to supply the inductor, input and output caps, and possibly a charge pump cap for making a higher voltage to drive the FET switch gate with. The datasheet will give you all the details. Read it carefully, then do what it says.

Multiple manufacturers should have products that do what you want. Some of the usual suspects are TI, Microchip, and Linear.

History
Why does this post require attention from curators or moderators?
You might want to add some details to your flag.

0 comment threads

+0
−0

One common solution for some 3 LDO's is to use a Buck regulator followed by a very low dropout PFET linear regulator combined into one part. IC's with very low V logic-level FETs (Vt=0.65) are used in a 1.2V supply. Low noise is preferred for Vref and Va on ADCs used by some uC's.

The voltage ratio (%Vo/Vin) is a good estimate of the efficiency for LDO's except for some minimum load current required.

The choice comes down to your specs for; cost, complexity, efficiency and ripple. Low ripple SMPS demand the utmost care in following design guidelines from the OEM for BOM selection, cooling and power layout.

History
Why does this post require attention from curators or moderators?
You might want to add some details to your flag.

0 comment threads

Sign up to answer this question »