How does JFET biasing work in a 2-terminal electret condenser microphone?
I’m trying to understand the biasing of a 2-terminal electret condenser microphone. The inner workings of a 2-terminal electret microphone are always drawn without a resistor at the JFET source. Is it supposed to be biased like a JFET in a self-bias configuration? If so, how would that work without a source resistor? Or, is there a source resistor and it’s omitted from diagrams for brevity?
general scheme for a JFET in a self-biased configuration (adapted from here, same in pdf):
For context, the microphone which I’d like to use is Knowles EK-23133-C36. It’s a 3-terminal electret mic. I’d like to wire it in a 2-terminal (common-source) configuration, because I've read that 2-terminal configuration is more sensitive at low sound pressure level.
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The voltages from the raw microphone are quite small and fairly high impedance. That's why an amplifier at the mic is needed in the first place. The signal on the wire would be way too small compared to noise in normal environments. The FET is a simple amplifier that increases the voltage and decreases the impedance to make it feasible to send the signal on a long (compared to the mm or so between the mic and the FET) cable.
The simplest and cheapest thing for the microphone manufacturer to do is to add the FET, make sure the gate can't drift to a non-zero DC voltage, and make the rest your problem. Actually it's not much of a problem. They could integrate the drain resistor, but then you'd have to run three wires to the whole microphone. By leaving the drain open, you have to put the pullup resistor in your circuit, but only need to run two wires to the microphone assembly.
The FET is designed to pass a small current when the gate is held at 0 V. The actual gate voltage variations are so tiny that the FET is essentially always at this simple bias point. The AC signal with a typical 3.3 kΩ drain resistance is still only a few mV. Since the AC variations from the bias point are so tiny, almost any bias point will do.
2-terminal configuration is more sensitive at low sound pressure level
That makes no sense. The same circuit is used both ways. The only difference is which end of the cable the pullup resistor is on.
With the pullup integrated into the microphone assembly, which ends up requiring a 3-wire cable, the manufacturer has more control over the parameters. It also gives the manufacturer the option to trim or customize the pullup to compensate for the inevitable variations from FET to FET. That could allow them to specify a more predictable gain, possibly better linearity, and the like. I don't know how much of that is actually done.
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If so, how would that work without a source resistor?
Quite well actually. If you look at the 2SK1109 you'll see that it has this characteristic: -
I've highlighted the zero voltage bias point with a red rectangle. This is the situation you get when there is no source resistor. The drain current is about 60 to 75 μA over a range of drain voltages from 1 volt to 10 volts and, of course, if you have a signal on your gate, it will "modulate" the drain current up and down and this will be seen as a voltage waveform across the external drain pull-up resistor.
This JFET is particularly suited to electret capsules because it only consumes tens to hundreds of microamps when quiescent. That as a specification is called $I_{DSS}$ and you want it to be generally sub 1 mA or you are just wasting power (especially important for battery applications).
What circuit voltage gain will you get with a 1 kΩ drain resistor?
The data sheet says that the forward transconductance is 1000 μS <-- that 1000 micro-siemens in case you thought it said micro-seconds. That is equivalent to 1 μA per millivolt meaning if you move the gate up and down a mV then the drain current is moved up and down by 1 μA. Into a 1 kΩ drain resistor that's a signal level of +/-1 mV.
You might say at this point that the voltage gain is unity (i.e. 1 mV change on the gate is 1 mV change on the drain) and, you'd be right but importantly, you have buffered the very weak and susceptible signal produced by the electret capsule with the JFET. Of course, if you used a 6k8 drain resistor then the voltage gain is 6.8 and, if you pick a JFET with a larger $I_{DSS}$ then you will also get more gain.
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