Is using different valued bypass capacitors a cargo cult? Should I do it because that's what everybody else does?
A microcontroller can be modelled simplistically as a broad band current source/sink. For example, when the microcontroller wakes up from sleep mode and goes into an application mode where many of its pins need to be pulled HIGH, the waveform for the current that the IC draws from the supply looks almost like a step function (a signal that contains all frequencies). Because the trace that connects the supply voltage to the IC's power pins have inductance, a sudden change in current leads to spikes in the supply voltage. To mitigate these spikes, bypass/decoupling capacitors to ground are placed next to the power pin.
The effect of this is shown in the two simulations below: one where the cap is placed "far" away from the controller's power pin, and the other where the cap is placed "closer" to the pin. Ls1 is the inductance from supply to bypass cap, and Ls2 is the inductance from bypass cap to the IC's power pin. The microcontroller is modelled as a pulsing current source, and the bypass capacitor is set to 100 nF. The blue curve is the drawn current; the red curve is the voltage at the IC's power pin.
The simulations show that it is a good idea to place the caps as close as possible.
Usually in datasheets they show multiple bypass capacitors in parallel with the power pin, and many times not with the same value. The argument for doing this seems to be that capacitors with different values and sizes have different frequency responses, so choosing a range of values should "cover all cases". But when I simulate this with simple parasitic capacitor models with values taken from real vendors, I find that using different valued capacitors make things worse, compared to parallel multiple capacitors of the same value:
The amplitude of the spikes is greater in the second simulation.
Is using different valued bypass capacitors just a "cargo cult"?
1 answer
If capacitors were ideal, then you would only need a single one as close between the power and ground pins as you can manage. 100 nF is generally sufficient, since the capacitor is only for holding the voltage steady during short-term events. Over the longer term, the power feed from the more distant supply catches up.
However, real capacitors are not ideal. They all have a frequency above which they no longer act like capacitors. Their impedance actually goes up with increased frequency after that point, whereas the impedance of an ideal capacitor decreases with increasing frequency forever.
It turns out that capacitors with a lower capacitance value can be made to work to higher frequencies. The impedance of a 1 nF capacitor is 100 times higher than that of a 100 nF capacitor when both are functioning like capacitors. However, at some frequency the impedance of the 100 nF cap will start going up with higher frequency, whereas that of the 1 nF continues to go down. The result is that there are some frequencies where the 1 nF cap actually has lower impedance than the 100 nF cap. Therefore paralleling the two keeps the impedance low over a wider frequency range.
For most ordinary microcontrollers, a single 100 nF or even 1 µF cap on each power pin is good enough. Note that today's 1 µF multi-layer ceramic surface mount caps have less impedance across the whole frequency range than the common 100 nF leaded disk caps from the 1980s where they were placed next to every thru-hole digital chip.
In some cases the extra high frequency range from paralleling caps with different characteristics actually matters. About 20 years ago, I specified a particular model of 100 pF cap as the first (closest) bypass cap to an RF chip that would handle over 400 MHz. I carefully looked at a bunch of datasheets to find the cap with the lowest impedance at that frequency.
So why do you seem to get contrary results? First, you really should be looking at this in the frequency domain. The size of a glitch from a time domain simulator doesn't mean much. Second, knowing all the real-world non-ideal characteristics of your caps, the board traces, and the dielectric of the board if practically impossible. Third, these effects are very short. Was your simulator really set up to correctly model things that change meaningfully at sub-nanosecond times?
Get your nose out of the simulator and think about the real world instead.
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