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I recently read the accepted answer here, by Olin Lathrop: Decoupling caps, PCB layout It talks about preventing an IC from acting as a center fed patch antenna by keeping the high frequency curre...
#3: Post edited
by
Carl
·
2025-10-15T10:41:21Z (11 months ago)
- I recently read the accepted answer here, by Olin Lathrop: [Decoupling caps, PCB layout](https://electronics.stackexchange.com/questions/15135/decoupling-caps-pcb-layout/15143#15143)
- It talks about preventing an IC from acting as a center fed patch antenna by keeping the high frequency currents generated by the IC off the global ground plane. This is achieved by using localized bypassing and local power and ground nets. The local power and ground net should be tied to the global power net and global ground plane only at one point.
- I think I understand the contents of the answer, but I want to make sure I get the implementation right.
- The thing I'm most uncertain about is **where** to tie the two nets together.
- Here I've created an artificial example: A voltage regulator delivering global power (VDD_GLOBAL and GND_GLOBAL); a locally bypassed microcontroller using local nets (VDD_IC, GND_IC), and two "net ties" to tie the nets together at one point.
- 
I believe this is the right way to implement the local nets and bypassing, as described in Olin's answer. Here is the layout, where I have connected the global ground and power net from the regulator to the local power net of the IC, as the traces are on their way to the decoupling capacitors. The blue shade is the global ground plane on the bottom layer. I haven't put effort into the layout as this is an artificial example.- 
- Is this the correct way to do it? Is the net tie point appropriate, or should it be positioned differently, like under the microcontroller itself?
- I recently read the accepted answer here, by Olin Lathrop: [Decoupling caps, PCB layout](https://electronics.stackexchange.com/questions/15135/decoupling-caps-pcb-layout/15143#15143)
- It talks about preventing an IC from acting as a center fed patch antenna by keeping the high frequency currents generated by the IC off the global ground plane. This is achieved by using localized bypassing and local power and ground nets. The local power and ground net should be tied to the global power net and global ground plane only at one point.
- I think I understand the contents of the answer, but I want to make sure I get the implementation right.
- The thing I'm most uncertain about is **where** to tie the two nets together.
- Here I've created an artificial example: A voltage regulator delivering global power (VDD_GLOBAL and GND_GLOBAL); a locally bypassed microcontroller using local nets (VDD_IC, GND_IC), and two "net ties" to tie the nets together at one point.
- 
- I believe this is the right way to implement the local nets and bypassing, as described in Olin's answer.
- Here is the layout and routing. I have connected the global ground and power net from the regulator to the local power net of the IC as the traces are on their way to the decoupling capacitors. The blue shade is the global ground plane on the bottom layer. I haven't put effort into the layout as this is an artificial example.
- 
- Is this the correct way to do it? Is the net tie point appropriate, or should it be positioned differently, like under the microcontroller itself?
#2: Post edited
by
Carl
·
2025-10-15T09:10:37Z (11 months ago)
- I recently read the accepted answer here, by Olin Lathrop: [Decoupling caps, PCB layout](https://electronics.stackexchange.com/questions/15135/decoupling-caps-pcb-layout/15143#15143)
- It talks about preventing an IC from acting as a center fed patch antenna by keeping the high frequency currents generated by the IC off the global ground plane. This is achieved by using localized bypassing and local power and ground nets. The local power and ground net should be tied to the global power net and global ground plane only at one point.
- I think I understand the contents of the answer, but I want to make sure I get the implementation right.
- The thing I'm most uncertain about is **where** to tie the two nets together.
Here I've created an artificial example: A voltage regulator delivering global power; a locally bypassed microcontroller using local nets, and two "net ties" to tie the nets together at one point.- 
- I believe this is the right way to implement the local nets and bypassing, as described in Olin's answer. Here is the layout, where I have connected the global ground and power net from the regulator to the local power net of the IC, as the traces are on their way to the decoupling capacitors. The blue shade is the global ground plane on the bottom layer. I haven't put effort into the layout as this is an artificial example.
- 
- Is this the correct way to do it? Is the net tie point appropriate, or should it be positioned differently, like under the microcontroller itself?
- I recently read the accepted answer here, by Olin Lathrop: [Decoupling caps, PCB layout](https://electronics.stackexchange.com/questions/15135/decoupling-caps-pcb-layout/15143#15143)
- It talks about preventing an IC from acting as a center fed patch antenna by keeping the high frequency currents generated by the IC off the global ground plane. This is achieved by using localized bypassing and local power and ground nets. The local power and ground net should be tied to the global power net and global ground plane only at one point.
- I think I understand the contents of the answer, but I want to make sure I get the implementation right.
- The thing I'm most uncertain about is **where** to tie the two nets together.
- Here I've created an artificial example: A voltage regulator delivering global power (VDD_GLOBAL and GND_GLOBAL); a locally bypassed microcontroller using local nets (VDD_IC, GND_IC), and two "net ties" to tie the nets together at one point.
- 
- I believe this is the right way to implement the local nets and bypassing, as described in Olin's answer. Here is the layout, where I have connected the global ground and power net from the regulator to the local power net of the IC, as the traces are on their way to the decoupling capacitors. The blue shade is the global ground plane on the bottom layer. I haven't put effort into the layout as this is an artificial example.
- 
- Is this the correct way to do it? Is the net tie point appropriate, or should it be positioned differently, like under the microcontroller itself?
#1: Initial revision
by
Carl
·
2025-10-15T09:09:26Z (11 months ago)
Using local power and ground net to keep high frequency currents off global ground plane
I recently read the accepted answer here, by Olin Lathrop: [Decoupling caps, PCB layout](https://electronics.stackexchange.com/questions/15135/decoupling-caps-pcb-layout/15143#15143) It talks about preventing an IC from acting as a center fed patch antenna by keeping the high frequency currents generated by the IC off the global ground plane. This is achieved by using localized bypassing and local power and ground nets. The local power and ground net should be tied to the global power net and global ground plane only at one point. I think I understand the contents of the answer, but I want to make sure I get the implementation right. The thing I'm most uncertain about is **where** to tie the two nets together. Here I've created an artificial example: A voltage regulator delivering global power; a locally bypassed microcontroller using local nets, and two "net ties" to tie the nets together at one point.  I believe this is the right way to implement the local nets and bypassing, as described in Olin's answer. Here is the layout, where I have connected the global ground and power net from the regulator to the local power net of the IC, as the traces are on their way to the decoupling capacitors. The blue shade is the global ground plane on the bottom layer. I haven't put effort into the layout as this is an artificial example.  Is this the correct way to do it? Is the net tie point appropriate, or should it be positioned differently, like under the microcontroller itself?