Post History
This a continuation of my previous question. As Olin suggested, I decided to simulate only Buck-Boost solution for powering my 16 bit ADC. Olin suggested me to add filtering at the output of the Bu...
#4: Post edited
by
newbie
·
2025-12-18T10:41:27Z (9 months ago)
- This a continuation of my previous [question](https://electrical.codidact.com/posts/295171). As Olin suggested, I decided to simulate only Buck-Boost solution for powering my 16 bit [ADC](https://www.analog.com/media/en/technical-documentation/data-sheets/ad5940-5941.pdf). Olin suggested me to add filtering at the output of the [Buck-Boost](https://www.analog.com/media/en/technical-documentation/data-sheets/3531fb.pdf) converter. My circuit diagram is given below.
- 
- Output waveforms and measured ripple voltage are shown below.
- **DVDD & IOVDD Rail:**
- 
- I am getting a ripple voltage of **7.5 mV** Peak-Peak.I believe this is not an issue with digital rail. Kindly confirm.
- **AVDD Rail:**
- 
- Here you can see that I am getting ripple of **8 mV** peak-Peak. The ADC is 16 bit and 1 LSB at 3.3 V = **≈50 µV.** The internal reference has ~60 dB PSRR, meaning it attenuates supply ripple by 1000. This shows that the allowed ripple at AVDD = 50 μV × 1000=**50 mV**.
- My measured ripple voltage at the powerline is **8 mV** Peak-Peak.
- Therefore the Ripple at ADC = (8 mV) / 1000 = **8 uV**.
- So I believe,I can go ahead with this design. May I know your thoughts.
- **Update:**
- In the previous simulation I have considered ESR of Capacitor only and the ESR I selected is 0.004 Ohm. In the below results I considered the ESR of Inductor (MSS4020-103ML) also and it is 0.21 Ohm. Please see the results below.
- In the digital rail I am getting a ripple of **41.4 mV** (Peak to Peak) and in the analog rail I am getting a ripple of **38 mV** (Peak to peak).
- **DVDD & IOVDD** :
- 
- **AVDD**:
- This a continuation of my previous [question](https://electrical.codidact.com/posts/295171). As Olin suggested, I decided to simulate only Buck-Boost solution for powering my 16 bit [ADC](https://www.analog.com/media/en/technical-documentation/data-sheets/ad5940-5941.pdf). Olin suggested me to add filtering at the output of the [Buck-Boost](https://www.analog.com/media/en/technical-documentation/data-sheets/3531fb.pdf) converter. My circuit diagram is given below.
- 
- Output waveforms and measured ripple voltage are shown below.
- **DVDD & IOVDD Rail:**
- 
- I am getting a ripple voltage of **7.5 mV** Peak-Peak.I believe this is not an issue with digital rail. Kindly confirm.
- **AVDD Rail:**
- 
- Here you can see that I am getting ripple of **8 mV** peak-Peak. The ADC is 16 bit and 1 LSB at 3.3 V = **≈50 µV.** The internal reference has ~60 dB PSRR, meaning it attenuates supply ripple by 1000. This shows that the allowed ripple at AVDD = 50 μV × 1000=**50 mV**.
- My measured ripple voltage at the powerline is **8 mV** Peak-Peak.
- Therefore the Ripple at ADC = (8 mV) / 1000 = **8 uV**.
- So I believe,I can go ahead with this design. May I know your thoughts.
- **Update:**
- In the previous simulation I have considered ESR of Capacitor only and the ESR I selected is 0.004 Ohm. In the below results I considered the ESR of Inductor (MSS4020-103ML) also and it is 0.21 Ohm. Please see the results below.
- In the digital rail I am getting a ripple of **41.4 mV** (Peak to Peak) and in the analog rail I am getting a ripple of **38 mV** (Peak to peak).
- **DVDD & IOVDD** :
- 
- **AVDD**:
- 
- May I know Can I go with BUCK-BOOST solution.
- Or Do I need to go with BUCK-BOOST + LDO Solution.
#3: Post edited
by
newbie
·
2025-12-18T09:22:02Z (9 months ago)
- This a continuation of my previous [question](https://electrical.codidact.com/posts/295171). As Olin suggested, I decided to simulate only Buck-Boost solution for powering my 16 bit [ADC](https://www.analog.com/media/en/technical-documentation/data-sheets/ad5940-5941.pdf). Olin suggested me to add filtering at the output of the [Buck-Boost](https://www.analog.com/media/en/technical-documentation/data-sheets/3531fb.pdf) converter. My circuit diagram is given below.
- 
- Output waveforms and measured ripple voltage are shown below.
- **DVDD & IOVDD Rail:**
- 
- I am getting a ripple voltage of **7.5 mV** Peak-Peak.I believe this is not an issue with digital rail. Kindly confirm.
- **AVDD Rail:**
- 
- Here you can see that I am getting ripple of **8 mV** peak-Peak. The ADC is 16 bit and 1 LSB at 3.3 V = **≈50 µV.** The internal reference has ~60 dB PSRR, meaning it attenuates supply ripple by 1000. This shows that the allowed ripple at AVDD = 50 μV × 1000=**50 mV**.
- My measured ripple voltage at the powerline is **8 mV** Peak-Peak.
- Therefore the Ripple at ADC = (8 mV) / 1000 = **8 uV**.
- So I believe,I can go ahead with this design. May I know your thoughts.
- **Update:**
In the previous simulation I have considered ESR of Capacitor only and the ESR I selected is 0.004 Ohm.In the below results I considered the ESR of Inductor (MSS4020-103ML) also and it is 0.21 Ohm. Please see the results below.- In the digital rail I am getting a ripple of **41.4 mV** (Peak to Peak) and in the analog rail I am getting a ripple of **38 mV** (Peak to peak).
- **DVDD & IOVDD** :
- 
- **AVDD**:
- 
- This a continuation of my previous [question](https://electrical.codidact.com/posts/295171). As Olin suggested, I decided to simulate only Buck-Boost solution for powering my 16 bit [ADC](https://www.analog.com/media/en/technical-documentation/data-sheets/ad5940-5941.pdf). Olin suggested me to add filtering at the output of the [Buck-Boost](https://www.analog.com/media/en/technical-documentation/data-sheets/3531fb.pdf) converter. My circuit diagram is given below.
- 
- Output waveforms and measured ripple voltage are shown below.
- **DVDD & IOVDD Rail:**
- 
- I am getting a ripple voltage of **7.5 mV** Peak-Peak.I believe this is not an issue with digital rail. Kindly confirm.
- **AVDD Rail:**
- 
- Here you can see that I am getting ripple of **8 mV** peak-Peak. The ADC is 16 bit and 1 LSB at 3.3 V = **≈50 µV.** The internal reference has ~60 dB PSRR, meaning it attenuates supply ripple by 1000. This shows that the allowed ripple at AVDD = 50 μV × 1000=**50 mV**.
- My measured ripple voltage at the powerline is **8 mV** Peak-Peak.
- Therefore the Ripple at ADC = (8 mV) / 1000 = **8 uV**.
- So I believe,I can go ahead with this design. May I know your thoughts.
- **Update:**
- In the previous simulation I have considered ESR of Capacitor only and the ESR I selected is 0.004 Ohm. In the below results I considered the ESR of Inductor (MSS4020-103ML) also and it is 0.21 Ohm. Please see the results below.
- In the digital rail I am getting a ripple of **41.4 mV** (Peak to Peak) and in the analog rail I am getting a ripple of **38 mV** (Peak to peak).
- **DVDD & IOVDD** :
- 
- **AVDD**:
- 
#2: Post edited
by
newbie
·
2025-12-18T09:21:26Z (9 months ago)
- This a continuation of my previous [question](https://electrical.codidact.com/posts/295171). As Olin suggested, I decided to simulate only Buck-Boost solution for powering my 16 bit [ADC](https://www.analog.com/media/en/technical-documentation/data-sheets/ad5940-5941.pdf). Olin suggested me to add filtering at the output of the [Buck-Boost](https://www.analog.com/media/en/technical-documentation/data-sheets/3531fb.pdf) converter. My circuit diagram is given below.
- 
- Output waveforms and measured ripple voltage are shown below.
- **DVDD & IOVDD Rail:**
- 
- I am getting a ripple voltage of **7.5 mV** Peak-Peak.I believe this is not an issue with digital rail. Kindly confirm.
- **AVDD Rail:**
- 
- Here you can see that I am getting ripple of **8 mV** peak-Peak. The ADC is 16 bit and 1 LSB at 3.3 V = **≈50 µV.** The internal reference has ~60 dB PSRR, meaning it attenuates supply ripple by 1000. This shows that the allowed ripple at AVDD = 50 μV × 1000=**50 mV**.
- My measured ripple voltage at the powerline is **8 mV** Peak-Peak.
- Therefore the Ripple at ADC = (8 mV) / 1000 = **8 uV**.
So I believe,I can go ahead with this design. May I know your thoughts.
- This a continuation of my previous [question](https://electrical.codidact.com/posts/295171). As Olin suggested, I decided to simulate only Buck-Boost solution for powering my 16 bit [ADC](https://www.analog.com/media/en/technical-documentation/data-sheets/ad5940-5941.pdf). Olin suggested me to add filtering at the output of the [Buck-Boost](https://www.analog.com/media/en/technical-documentation/data-sheets/3531fb.pdf) converter. My circuit diagram is given below.
- 
- Output waveforms and measured ripple voltage are shown below.
- **DVDD & IOVDD Rail:**
- 
- I am getting a ripple voltage of **7.5 mV** Peak-Peak.I believe this is not an issue with digital rail. Kindly confirm.
- **AVDD Rail:**
- 
- Here you can see that I am getting ripple of **8 mV** peak-Peak. The ADC is 16 bit and 1 LSB at 3.3 V = **≈50 µV.** The internal reference has ~60 dB PSRR, meaning it attenuates supply ripple by 1000. This shows that the allowed ripple at AVDD = 50 μV × 1000=**50 mV**.
- My measured ripple voltage at the powerline is **8 mV** Peak-Peak.
- Therefore the Ripple at ADC = (8 mV) / 1000 = **8 uV**.
- So I believe,I can go ahead with this design. May I know your thoughts.
- **Update:**
- In the previous simulation I have considered ESR of Capacitor only and the ESR I selected is 0.004 Ohm.In the below results I considered the ESR of Inductor (MSS4020-103ML) also and it is 0.21 Ohm. Please see the results below.
- In the digital rail I am getting a ripple of **41.4 mV** (Peak to Peak) and in the analog rail I am getting a ripple of **38 mV** (Peak to peak).
- **DVDD & IOVDD** :
- 
- **AVDD**:
- 
#1: Initial revision
by
newbie
·
2025-12-17T14:48:02Z (9 months ago)
Ripple calculation for Powering ADC
This a continuation of my previous [question](https://electrical.codidact.com/posts/295171). As Olin suggested, I decided to simulate only Buck-Boost solution for powering my 16 bit [ADC](https://www.analog.com/media/en/technical-documentation/data-sheets/ad5940-5941.pdf). Olin suggested me to add filtering at the output of the [Buck-Boost](https://www.analog.com/media/en/technical-documentation/data-sheets/3531fb.pdf) converter. My circuit diagram is given below.  Output waveforms and measured ripple voltage are shown below. **DVDD & IOVDD Rail:**  I am getting a ripple voltage of **7.5 mV** Peak-Peak.I believe this is not an issue with digital rail. Kindly confirm. **AVDD Rail:**  Here you can see that I am getting ripple of **8 mV** peak-Peak. The ADC is 16 bit and 1 LSB at 3.3 V = **≈50 µV.** The internal reference has ~60 dB PSRR, meaning it attenuates supply ripple by 1000. This shows that the allowed ripple at AVDD = 50 μV × 1000=**50 mV**. My measured ripple voltage at the powerline is **8 mV** Peak-Peak. Therefore the Ripple at ADC = (8 mV) / 1000 = **8 uV**. So I believe,I can go ahead with this design. May I know your thoughts.