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I am using the STM32WBA5MMG module in my design. The reference design is the MB2131 STM32WBA5M M.2 expansion board from ST (schematic), and the external debug connector sheet contains the note: ...
#7: Question reopened
by
Olin Lathrop
·
2026-01-20T14:09:06Z (8 months ago)
#6: Post edited
by
Nick Alexeev
·
2026-01-19T18:10:32Z (8 months ago)
I am using the [STM32WBA5MMG](https://www.st.com/resource/en/datasheet/stm32wba5mmg.pdf) module in my design. The reference design is the [MB2131 STM32WBA5M M.2](https://www.st.com/resource/en/schematic_pack/mb2131-wba5m-b02-schematic.pdf) expansion board from ST, and the external debug connector sheet contains the note:**“Specific constraints for SWDIO and SWCLK (must have same length and must be shielded).”**- An excerpt of that schematic is attached, showing the STDC14 receiver connector and the SWD signals.
- I have two questions:
- SWDIO and SWCLK are single‑ended (not a differential pair), so why is explicit length matching between these two signals required on the PCB? Is this just to minimize clock‑to‑data skew at higher SWD clock frequencies, or is there another reason?
- The note also says the lines “must be shielded”. Does this simply mean routing SWDIO and SWCLK over a solid ground plane (with a good reference return and maybe some ground stitching vias near the connector), or is a more specific shielding topology implied (e.g., guard traces, ground‑surrounded microstrip, etc.)?
- Any guidance on how strictly these constraints need to be followed (for example, acceptable length mismatch on a short board and typical SWD clock speeds) would be appreciated.
>
- I am using the [STM32WBA5MMG](https://www.st.com/resource/en/datasheet/stm32wba5mmg.pdf) module in my design. The reference design is the [MB2131 STM32WBA5M M.2 expansion board from ST](https://www.st.com/en/evaluation-tools/b-wba5m-wpan.html#overview) ([schematic](https://www.st.com/resource/en/schematic_pack/mb2131-wba5m-b02-schematic.pdf)), and the external debug connector sheet contains the note:
- > Specific constraints for SWDIO and SWCLK (must have same length and must be shielded).
- [p.5 in the [schematic](https://www.st.com/resource/en/schematic_pack/mb2131-wba5m-b02-schematic.pdf) ]
- An excerpt of that schematic is attached, showing the STDC14 receiver connector and the SWD signals.
- I have two questions:
- SWDIO and SWCLK are single‑ended (not a differential pair), so why is explicit length matching between these two signals required on the PCB? Is this just to minimize clock‑to‑data skew at higher SWD clock frequencies, or is there another reason?
- The note also says the lines “must be shielded”. Does this simply mean routing SWDIO and SWCLK over a solid ground plane (with a good reference return and maybe some ground stitching vias near the connector), or is a more specific shielding topology implied (e.g., guard traces, ground‑surrounded microstrip, etc.)?
- Any guidance on how strictly these constraints need to be followed (for example, acceptable length mismatch on a short board and typical SWD clock speeds) would be appreciated.
- 
#5: Post edited
by
newbie
·
2026-01-19T14:27:08Z (8 months ago)
- I am using the [STM32WBA5MMG](https://www.st.com/resource/en/datasheet/stm32wba5mmg.pdf) module in my design. The reference design is the [MB2131 STM32WBA5M M.2](https://www.st.com/resource/en/schematic_pack/mb2131-wba5m-b02-schematic.pdf) expansion board from ST, and the external debug connector sheet contains the note:
“Specific constraints for SWDIO and SWCLK (must have same length and must be shielded).”- An excerpt of that schematic is attached, showing the STDC14 receiver connector and the SWD signals.
- I have two questions:
- SWDIO and SWCLK are single‑ended (not a differential pair), so why is explicit length matching between these two signals required on the PCB? Is this just to minimize clock‑to‑data skew at higher SWD clock frequencies, or is there another reason?
- The note also says the lines “must be shielded”. Does this simply mean routing SWDIO and SWCLK over a solid ground plane (with a good reference return and maybe some ground stitching vias near the connector), or is a more specific shielding topology implied (e.g., guard traces, ground‑surrounded microstrip, etc.)?
- Any guidance on how strictly these constraints need to be followed (for example, acceptable length mismatch on a short board and typical SWD clock speeds) would be appreciated.
- 
- >
- I am using the [STM32WBA5MMG](https://www.st.com/resource/en/datasheet/stm32wba5mmg.pdf) module in my design. The reference design is the [MB2131 STM32WBA5M M.2](https://www.st.com/resource/en/schematic_pack/mb2131-wba5m-b02-schematic.pdf) expansion board from ST, and the external debug connector sheet contains the note:
- **“Specific constraints for SWDIO and SWCLK (must have same length and must be shielded).”**
- An excerpt of that schematic is attached, showing the STDC14 receiver connector and the SWD signals.
- I have two questions:
- SWDIO and SWCLK are single‑ended (not a differential pair), so why is explicit length matching between these two signals required on the PCB? Is this just to minimize clock‑to‑data skew at higher SWD clock frequencies, or is there another reason?
- The note also says the lines “must be shielded”. Does this simply mean routing SWDIO and SWCLK over a solid ground plane (with a good reference return and maybe some ground stitching vias near the connector), or is a more specific shielding topology implied (e.g., guard traces, ground‑surrounded microstrip, etc.)?
- Any guidance on how strictly these constraints need to be followed (for example, acceptable length mismatch on a short board and typical SWD clock speeds) would be appreciated.
- 
- >
#4: Post edited
by
newbie
·
2026-01-19T14:10:32Z (8 months ago)
I am using [STM32WBA5MMG](https://www.st.com/resource/en/datasheet/stm32wba5mmg.pdf) in my design. This the development board schematic. Below image is from development [board schematic](https://www.st.com/resource/en/schematic_pack/mb2131-wba5m-b02-schematic.pdf).As per the constrains , SWDIO and SWCLK must be length matched. Also need to provide a shield. My questions are given below.1. SWDIO and SWCLK are not differential lines, why length matching is required for them.1. By shield did they mean routing SWDIO and SWCLK on top of a solid GND plane1. Why there is a 100 Ohm resistor on GNDDetect
- I am using the [STM32WBA5MMG](https://www.st.com/resource/en/datasheet/stm32wba5mmg.pdf) module in my design. The reference design is the [MB2131 STM32WBA5M M.2](https://www.st.com/resource/en/schematic_pack/mb2131-wba5m-b02-schematic.pdf) expansion board from ST, and the external debug connector sheet contains the note:
- “Specific constraints for SWDIO and SWCLK (must have same length and must be shielded).”
- An excerpt of that schematic is attached, showing the STDC14 receiver connector and the SWD signals.
- I have two questions:
- SWDIO and SWCLK are single‑ended (not a differential pair), so why is explicit length matching between these two signals required on the PCB? Is this just to minimize clock‑to‑data skew at higher SWD clock frequencies, or is there another reason?
- The note also says the lines “must be shielded”. Does this simply mean routing SWDIO and SWCLK over a solid ground plane (with a good reference return and maybe some ground stitching vias near the connector), or is a more specific shielding topology implied (e.g., guard traces, ground‑surrounded microstrip, etc.)?
- Any guidance on how strictly these constraints need to be followed (for example, acceptable length mismatch on a short board and typical SWD clock speeds) would be appreciated.
- 
- >
#3: Question closed
by
Olin Lathrop
·
2026-01-19T13:50:28Z (8 months ago)
#2: Post edited
by
newbie
·
2026-01-19T13:22:13Z (8 months ago)
- I am using [STM32WBA5MMG](https://www.st.com/resource/en/datasheet/stm32wba5mmg.pdf) in my design. This the development board schematic. Below image is from development [board schematic](https://www.st.com/resource/en/schematic_pack/mb2131-wba5m-b02-schematic.pdf).
- 
- As per the constrains , SWDIO and SWCLK must be length matched. Also need to provide a shield. My questions are given below.
- 1. SWDIO and SWCLK are not differential lines, why length matching is required for them.
1. By shield did they mean routing SWDIO and SWCLK on top of a solid GND plane
- I am using [STM32WBA5MMG](https://www.st.com/resource/en/datasheet/stm32wba5mmg.pdf) in my design. This the development board schematic. Below image is from development [board schematic](https://www.st.com/resource/en/schematic_pack/mb2131-wba5m-b02-schematic.pdf).
- 
- As per the constrains , SWDIO and SWCLK must be length matched. Also need to provide a shield. My questions are given below.
- 1. SWDIO and SWCLK are not differential lines, why length matching is required for them.
- 1. By shield did they mean routing SWDIO and SWCLK on top of a solid GND plane
- 1. Why there is a 100 Ohm resistor on GNDDetect
#1: Initial revision
by
newbie
·
2026-01-19T13:11:59Z (8 months ago)
Need clarification on SWDIO/SWCLK length‑matching and “shielding” for STM32WBA5MMG debug connector
I am using [STM32WBA5MMG](https://www.st.com/resource/en/datasheet/stm32wba5mmg.pdf) in my design. This the development board schematic. Below image is from development [board schematic](https://www.st.com/resource/en/schematic_pack/mb2131-wba5m-b02-schematic.pdf).  As per the constrains , SWDIO and SWCLK must be length matched. Also need to provide a shield. My questions are given below. 1. SWDIO and SWCLK are not differential lines, why length matching is required for them. 1. By shield did they mean routing SWDIO and SWCLK on top of a solid GND plane