Post History
Important: I know nothing about how to design a PCB or any of the jargon related to PCB designing I am following a tutorial titled Switching Loop Layout by Prof. Alex Hanson for Texas Instruments ...
#2: Post edited
by
ankit.kumar
·
2026-03-03T14:48:11Z (7 months ago)
- Important: I know nothing about how to design a PCB or any of the jargon related to PCB designing
- I am following a tutorial titled [Switching Loop Layout](https://www.ti.com/video/6244751953001?keyMatch=switching%20loop%20layout&tisearch=universal_search) by Prof. Alex Hanson for Texas Instruments to design my PCB.
- At 7 minutes and 58 seconds Prof. Hanson mentions the impact of loop-area and loop-depth on parasitic inductance offered by a loop.
- **Screenshot 1**
- 
- Referring to the drawing enclosed in the green box of screenshot 1:
- Area enclosed by the loop = A (the blue hatched section)
- Depth of the loop = d (thickness of the copper)
- Then, at 9 minutes and 8 seconds the Prof. mentions another loop formed by folding a copper strip.
- **Screenshot 2**
- 
- Looking at the copper strip enclosed in the green box in screenshot 2:
- Area of the loop = A (area enclosed by the copper strips, in blue)
- Depth of the loop = d (width of the copper strip)
- Going by this logic he analyses three loops (one planar loop and two vertical loops).
- **Screenshot 3**
- 
- Later in the tutorial he explains:
- Planar Loop has the minimum depth (~ a few µm) and therefore would produce the highest parasitic inductance.
- Vertical Loop 1 is on a 2-layer PCB and its depth is the height of the PCB (~ a few mm), therefore, its parasitic inductance would be much lesser than the planar's.
Vertical Loop 2 is on a 4-layer PCB and its depth is roughly 14- of vertical loop 1's, therefore its inductance will be smaller than vertical loop 1's (refer screenshot 4 and 5 below).
- **Screenshot 4**
- 
- **Screenshot 5**
- 
- I do not doubt the knowledge of the speaker, however, could it be possible that he jumbled his words and instead of saying vertical loop 1 is better than vertical loop 2, he spoke the opposite? Out of the two vertical loops which will yield a smaller parasitic inductance?
- I seek the opinion of the experts.
- PS: He has taken the example of solenoids in a crude manner to explain the concept in a general manner. Please do not be harsh about that part.
- Important: I know nothing about how to design a PCB or any of the jargon related to PCB designing
- I am following a tutorial titled [Switching Loop Layout](https://www.ti.com/video/6244751953001?keyMatch=switching%20loop%20layout&tisearch=universal_search) by Prof. Alex Hanson for Texas Instruments to design my PCB.
- At 7 minutes and 58 seconds Prof. Hanson mentions the impact of loop-area and loop-depth on parasitic inductance offered by a loop.
- **Screenshot 1**
- 
- Referring to the drawing enclosed in the green box of screenshot 1:
- Area enclosed by the loop = A (the blue hatched section)
- Depth of the loop = d (thickness of the copper)
- Then, at 9 minutes and 8 seconds the Prof. mentions another loop formed by folding a copper strip.
- **Screenshot 2**
- 
- Looking at the copper strip enclosed in the green box in screenshot 2:
- Area of the loop = A (area enclosed by the copper strips, in blue)
- Depth of the loop = d (width of the copper strip)
- Going by this logic he analyses three loops (one planar loop and two vertical loops).
- **Screenshot 3**
- 
- Later in the tutorial he explains:
- Planar Loop has the minimum depth (~ a few µm) and therefore would produce the highest parasitic inductance.
- Vertical Loop 1 is on a 2-layer PCB and its depth is the height of the PCB (~ a few mm), therefore, its parasitic inductance would be much lesser than the planar's.
- Vertical Loop 2 is on a 4-layer PCB and its depth is roughly \$\frac{1}{4}\$
- of vertical loop 1's, therefore its inductance will be smaller than vertical loop 1's (refer screenshot 4 and 5 below).
- **Screenshot 4**
- 
- **Screenshot 5**
- 
- I do not doubt the knowledge of the speaker, however, could it be possible that he jumbled his words and instead of saying vertical loop 1 is better than vertical loop 2, he spoke the opposite? Out of the two vertical loops which will yield a smaller parasitic inductance?
- I seek the opinion of the experts.
- PS: He has taken the example of solenoids in a crude manner to explain the concept in a general manner. Please do not be harsh about that part.
#1: Initial revision
by
ankit.kumar
·
2026-03-03T12:13:35Z (7 months ago)
Laying out Switching Loops on PCB for Minimum Loop Area and Parasitic Inductance
Important: I know nothing about how to design a PCB or any of the jargon related to PCB designing I am following a tutorial titled [Switching Loop Layout](https://www.ti.com/video/6244751953001?keyMatch=switching%20loop%20layout&tisearch=universal_search) by Prof. Alex Hanson for Texas Instruments to design my PCB. At 7 minutes and 58 seconds Prof. Hanson mentions the impact of loop-area and loop-depth on parasitic inductance offered by a loop. **Screenshot 1**  Referring to the drawing enclosed in the green box of screenshot 1: Area enclosed by the loop = A (the blue hatched section) Depth of the loop = d (thickness of the copper) Then, at 9 minutes and 8 seconds the Prof. mentions another loop formed by folding a copper strip. **Screenshot 2**  Looking at the copper strip enclosed in the green box in screenshot 2: Area of the loop = A (area enclosed by the copper strips, in blue) Depth of the loop = d (width of the copper strip) Going by this logic he analyses three loops (one planar loop and two vertical loops). **Screenshot 3**  Later in the tutorial he explains: Planar Loop has the minimum depth (~ a few µm) and therefore would produce the highest parasitic inductance. Vertical Loop 1 is on a 2-layer PCB and its depth is the height of the PCB (~ a few mm), therefore, its parasitic inductance would be much lesser than the planar's. Vertical Loop 2 is on a 4-layer PCB and its depth is roughly 14 of vertical loop 1's, therefore its inductance will be smaller than vertical loop 1's (refer screenshot 4 and 5 below). **Screenshot 4**  **Screenshot 5**  I do not doubt the knowledge of the speaker, however, could it be possible that he jumbled his words and instead of saying vertical loop 1 is better than vertical loop 2, he spoke the opposite? Out of the two vertical loops which will yield a smaller parasitic inductance? I seek the opinion of the experts. PS: He has taken the example of solenoids in a crude manner to explain the concept in a general manner. Please do not be harsh about that part.