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PWM Triangle Wave from two clocks

What follows is a proposed concept of a simple (in principle!) way to generate a fixed-amplitude triangle wave, using two clocks, an XOR gate, and not using any processor cycles.
It is practical in the low-mid-100-Hz ballpark, with typical mcu clocks. Motivating application is dither waveform for solenoid valve control signals.
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SUMMARY
Two timers output two clocks A, B, with fixed 50% duty cycle. XOR(A,B) produces a symmetrical PWM triangle wave, with modulation frequency at (f_A + f_B), and triangle frequency at (f_A - f_B). No other additional hardware. Illustrated below -- the resulting waveform on the bottom is a PWM. (click to zoom)
[![xor-pwm](https://electrical.codidact.com/uploads/6bdrMJQBbLLbZvD8EJo2Fq1L)
](https://electrical.codidact.com/uploads/6bdrMJQBbLLbZvD8EJo2Fq1L)
~~Given a master clock f_cpu, the available triangle frequencies are 2 * f_cpu / (n^2 - 1), where “n” is an odd integer. The two clocks are set to f_cpu/(n+1) and f_cpu/(n-1).~~
The low-pass filter design is also parametrized by “n”. If we define passband at the triangle’s 5th harmonic, then nondimensional value (f_stop / f_pass), representing the transition band, comes out to n/5.
The nondimensional transition band corresponds to "filter complexity". A narrower transition band places more demands on the filter design. Given a lower limit of this value, the practical upper limit for the triangle frequency can then be derived relative to f_cpu, as (2/25)/(f_stop/f_pass)^2 . Typical values shown below.
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Practical limit of f_triangle
| min acceptable (f_stop / f_pass) | max (f_triangle / f_cpu) |
|- | - |
| 20 | 1 / 5000 |
| 40 | 1 / 20000 |
| 60 (recommended) | 1 / 45000 |
| 80 | 1 / 80000 |
| 100 | 1 / 125000 |
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Example Circuit producing 199Hz from 10MHz f_cpu
![example-circuit](https://electrical.codidact.com/uploads/26hXXxCXxva2uwpAz1aunkny)
Simulation of above circuit. 0-1V inputs produce 12mV - 988 mV peaks
![simulation-full-scale](https://electrical.codidact.com/uploads/xR9jysiCP1fK71oD4GdR3zt3)
Detail showing less than 1% ripple.
![simulation-ripple-detail](https://electrical.codidact.com/uploads/qo7hVPncmZSqnFfKoRw7SEzr)
-----
Additional details of the analysis, and example showing the design calculation, are [here (pdf file, 5 pages)](https://gofile.io/d/hMXWWc). I don't know this site's markup features well enough yet to get it the local format easily...

What follows is a proposed concept of a simple (in principle!) way to generate a fixed-amplitude triangle wave, using two clocks, an XOR gate, and not using any processor cycles.
It is practical in the low-mid-100-Hz ballpark, with typical mcu clocks. Motivating application is dither waveform for solenoid valve control signals.
----
SUMMARY
Two timers output two clocks A, B, with fixed 50% duty cycle. XOR(A,B) produces a symmetrical PWM triangle wave, with modulation frequency at the sum of the f_A and f_B, and triangle frequency at the difference. No other additional hardware. Illustrated below -- the resulting waveform on the bottom is a PWM. (click to zoom)
[![xor-pwm](https://electrical.codidact.com/uploads/6bdrMJQBbLLbZvD8EJo2Fq1L)
](https://electrical.codidact.com/uploads/6bdrMJQBbLLbZvD8EJo2Fq1L)
Given a master clock f_cpu, the available triangle frequencies are
$2 f_{\rm cpu} / (n^2 - 1)$, where “n” is an odd integer. The two clocks are set to $f_{\rm cpu}/(n+1)$ and $f_{\rm cpu}/(n-1)$.
The low-pass filter design is also parametrized by “n”. If we define passband at the triangle’s 5th harmonic, then non dimensional value (f_stop / f_pass), representing the transition band, comes out to n/5.
The non dimensional transition band corresponds to "filter complexity". A narrower transition band places more demands on the filter design. Given a lower limit of this value, the practical upper limit for the triangle frequency can then be derived relative to f_cpu, as $$\frac{2 f_{\rm pass}^2}{25 f_{\rm stop}^2}.$$
Typical values shown below.
----
Practical limit of f_triangle
| min acceptable (f_stop / f_pass) | max (f_triangle / f_cpu) |
|- | - |
| 20 | 1 / 5000 |
| 40 | 1 / 20000 |
| 60 (recommended) | 1 / 45000 |
| 80 | 1 / 80000 |
| 100 | 1 / 125000 |
-----
Example Circuit producing 199Hz from 10MHz f_cpu
![example-circuit](https://electrical.codidact.com/uploads/26hXXxCXxva2uwpAz1aunkny)
Simulation of above circuit. 0-1V inputs produce 12mV - 988 mV peaks
![simulation-full-scale](https://electrical.codidact.com/uploads/xR9jysiCP1fK71oD4GdR3zt3)
Detail showing less than 1% ripple.
![simulation-ripple-detail](https://electrical.codidact.com/uploads/qo7hVPncmZSqnFfKoRw7SEzr)
-----
Additional details of the analysis, and example showing the design calculation, are [here (pdf file, 5 pages)](https://gofile.io/d/hMXWWc). The site format is a little limiting unfortunately.

microcontroller PWM waveform-generation triangle-wave

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