Activity for Mu3
| Type | On... | Excerpt | Status | Date |
|---|---|---|---|---|
| Edit | Post #281964 | Initial revision | — | over 3 years ago |
| Question | — |
What is the purpose of paralleling capacitors on the input/output of a power converter? In the design of a power converter, picking the appropriate capacitors for the input and output of the converter is quite important. It is relatively easy to calculate the necessary values for a given application. However, in many datasheets it is suggested to use a capacitor network instead of a ... (more) |
— | over 3 years ago |
| Comment | Post #281364 |
Interesting, I have looked at a few designs and they don't show a diode in parallel with the FET, although it would make sense to have one. The timing is indeed an issue, but there are many chips available on the market that handle the switching process (Analog Devices has some nice ones). So if I ha... (more) |
— | almost 4 years ago |
| Edit | Post #281361 |
Post edited: Clarified the question |
— | almost 4 years ago |
| Edit | Post #281361 | Initial revision | — | almost 4 years ago |
| Question | — |
Design considerations for a synchronous DC/DC converter In the field of DC/DC conversion, one can build a synchronous DC/DC converter (also referred to as synchronous rectification). This practice involves replacing a diode with a MOSFET switch. As far as I understand, this is a beneficial practice since the MOSFET will dissipate much less power than a... (more) |
— | almost 4 years ago |
| Comment | Post #281323 |
@coquelicot: if you give an answer that does not go in line to what was asked, it is hardly the fault of the one who asks. (more) |
— | almost 4 years ago |
| Edit | Post #281274 | Initial revision | — | almost 4 years ago |
| Answer | — |
A: Why 3.3V instead of 3V? This question popped up in the feed and I got curious. Here is what I could find. Note that I am not an IC engineer so my interpretation of some facts may be off. The 3.3V level is defined in the JESD8 standard. It was made by JEDEC. 3.3V is a stepping stone on the path of decreasing supply vol... (more) |
— | almost 4 years ago |
| Comment | Post #281092 |
Thanks for the response. I read the SE question, it also is quite insightful. (more) |
— | almost 4 years ago |
| Comment | Post #281070 |
Interesting, thanks for the answer. Yes, it seems that there are also multi-topology options, which does give me a wider range of chips to look at. I didn't know about LT not selling to Digikey - now I can find their chips there so I guess that debacle is over. Is there some sort of "chip database" w... (more) |
— | almost 4 years ago |
| Edit | Post #281069 | Initial revision | — | almost 4 years ago |
| Question | — |
Why do DC/DC switching controllers seem to favour the buck-boost topology over similar ones like Cuk, SEPIC and Zeta? I am looking at various DC/DC converter topologies for a power system I am designing. The most suitable topology for me is one that can perform both step-up and step-down functions, so I am looking into buck-boost and similar topologies like Cuk, SEPIC and Zeta. While selecting the candidate ICs f... (more) |
— | almost 4 years ago |
| Comment | Post #278854 |
The original question was indeed from an interested bystander. I don't see those kind of questions as harmful, they provide insight into different areas of EE. Closing these kind of question does not do anything but deter curiosity, especially for newcomers and students. (more) |
— | about 4 years ago |
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