High/low indication of power supply with linear post-regulator
This concept provides a simple high/low indication for the output voltage of a power supply that is followed by an LDO (low drop-out) linear post-regulator. A basic diagram of the system is:
The method presented here is particularly useful when the power supply is a switcher with a pulse on demand controller. The Sense block provides a digital signal indicating whether the power supply output is above or below its regulation threshold. When above, the controller does nothing. When below, the controller causes one more switching pulse to occur at the next opportunity.
The traditional Sense block is a comparator that compares the power supply output against a fixed reference voltage. The reference voltage and the comparison must be accurate enough to guarantee the lowest voltage between pulses is above the LDO's minimum input, but not so high that the LDO dissipates excessive power.
Some LDOs have low maximum input voltages. For example, the Microchip MCP1700 allows only 6 V maximum input. The 350 mV dropout leaves the valid input range for the 5 V version from 5.35 to 6.00 V. This can be stated as 5.68 V ±5.7%.
This may sound like a comfortable margin, but this error budget gets eaten up quickly. Let's say that due to the pulse on demand control method, the supply ripple is ±50 mV from the regulation threshold. Now the threshold must be 5.40 to 5.95 V, or 5.68 V ±4.85%.
This is admittedly not too hard to meet, but note that a 3% voltage reference, 1% divider resistors, and a few mV comparator offset pretty much use up the whole error budget. That leaves little room for 1% resistor values not providing the exact desired divider ratio.
The point is not that this is a difficult design constraint, but that what appears to be an "easy" drop in is tighter than it might first appear, and requires some considerations of all sources of error.
The innovation presented here solves the problem by transforming the Sense block from detecting against an absolute threshold, to a relative value above the LDO output. Put another way, the LDO drop voltage is sensed instead of its absolute input voltage.
The same 5.40 to 5.95 input voltage range as above, becomes a 0.40 to 0.95 drop range. When expressed as 0.68 V ±41%, it is apparent that much less accuracy can be tolerated.
The specific trick
Note that the 680 mV drop is close to one silicon junction drop. The trick is therefore to use the base-emitter junction of a PNP transistor as the comparator. That happens to work out well in this case where the LDO's maximum input voltage is less than a volt above its minimum. However, the roughly 700 mV of a silicon junction drop is a comfortable LDO drop voltage in many cases, even if the LDO could tolerate a larger input voltage.
Here is an example circuit:
Q1 turns on when its base is about 700 mV lower than its emitter. Since the E-B voltage is basically the LDO drop voltage, SENSE is pulled high when the switching power supply is above its target voltage. SENSE is left open when the switcher is below its target voltage.
A voltage divider to ground on SENSE can be used to make a logic signal of a particular voltage, as long as that voltage is roughly less then the LDO output.
During startup of the switching power supply, the SENSE line should not be pulled high because the switching pulses should not be stopped.
However, the output voltage of LDOs are generally not specified with the input voltage below some minimum level. This means, in theory, the LDO could leave its output voltage near ground until the input rises to the minimum guaranteed operating level.
Note that in the case of low input voltage, SENSE will not be driven as high as when the LDO is operating within specifications.
One solution is to adjust the resistor divider on SENSE so that during normal operation, the output of the divider is just above the guaranteed logic high input threshold of whatever is receiving the SENSE signal. Even that may not result in fully specified operation, since there is usually a considerable range between the maximum guaranteed logic low threshold and the minimum guaranteed logic high threshold, but stutter at startup is less likely.
In practice, I have not seen a single LDO that didn't drive its output to nearly its input when the input was low.
This method is particularly useful when the supply is isolated from the controller. In that case, the SENSE line show above can drive a opto-isolator with series resistor directly. Assuming an opto-isolator would be used either way, the only additional parts to implement the Sense block are two resistors and one transistor. Just about any small signal transistor is suitable, and the resistors need not have particularly tight tolerances.
Easy pulse on demand implementation
Switching power supplies controlled by the pulse on demand scheme may have higher ripple compared to other control schemes. But they are simple, inherently stable, and easy to implement. For these reasons when I'm not using a dedicated chip to implement a switching power supply, I usually use a pulse on demand controller.
A simple implementation I have used a number of times is to create the pulses with a spare PWM generator in a microcontroller that is already there for other reasons. A PWM generator and two I/O pins are often free, being unused otherwise. The PWM parameters are set to just keep up with the worst case output demand. The SENSE signal then drives the hardware shutdown to the PWM so that the pulses are stopped when the output voltage is above the regulation threshold. Once this is set up in the firmware, it runs completely on its own in hardware without further CPU cycles.
While I did discover this idea myself, I know that Russell McMahon on the PIC List developed it independently. Doubtless others have too.