Post History

#20: Post edited by Pete W‭ · 2020-12-30T18:19:39Z (over 3 years ago)

Raw

Markdown

• What follows is a proposed concept of a simple (in principle!) way to generate a fixed-amplitude triangle wave, using two clocks, an XOR gate, and not using any processor cycles.
• It is practical in the low-mid-100-Hz ballpark, with typical mcu clocks. Motivating application is dither waveform for solenoid valve control signals.
• ----
• SUMMARY
• Two timers output two clocks A, B, with fixed 50% duty cycle. XOR(A,B) produces a symmetrical PWM triangle wave, with modulation frequency at ($f_{\rm A} + f_{\rm B})$ , and triangle frequency at $(f_{\rm A} - f_{\rm B})$. No other additional hardware. Illustrated below, showing how the XOR output is equivalent to a PWM. (click to zoom)
• [
• ](https://electrical.codidact.com/uploads/6bdrMJQBbLLbZvD8EJo2Fq1L)
• Given a master clock $f_{\rm CPU}$, the available frequencies are:
• $$f_{\rm TRIANGLE} = \frac{2 f_{\rm CPU}}{(n^2 - 1)}$$
• "$n$" should be an odd integer. The two clocks are set to $f_{\rm CPU}/(n+1)$ and $f_{\rm CPU}/(n-1)$, to make the dividers even numbers, so that A and B can have 50% duty cycles.
• The low-pass filter design, and the limitations that result from it, are also parametrized by $n$. Let's define the passband at the triangle’s 5th harmonic, and the stopband at $(f_{ m A} + f_{ m B})$. The dimensionless value $f_{ m STOP} / f_{ m PASS}$ will represent the filter's transition band, and this value comes out to $n/5$.
• The dimensionless transition band corresponds to "filter complexity". A narrower transition band places more demands on the filter design. Given a lower limit of this value, a practical upper limit for the triangle frequency can then be derived as
• $$ \frac{f_{\rm TRIANGLE(max)}}{f_{\rm CPU}} = \frac{2}{25} \left(\frac{f_{\rm PASS}}{f_{\rm STOP}}\right)^2$$
• The table below uses this formula to show typical limits of the application:
• | min acceptable $f_{\rm STOP}/f_{\rm PASS}$ | max $f_{\rm TRIANGLE}/f_{\rm CPU}$ |
• |- | - |
• | 20 | 1 / 5000 |
• | 40 | 1 / 20000 |
• | 60 (shown in example) | 1 / 45000 |
• | 80 | 1 / 80000 |
• | 100 | 1 / 125000 |
• -----
• Example Circuit producing 199Hz from 10MHz f_cpu
• 
• Simulation of above circuit. 0-1V inputs produce 12mV - 988 mV peaks
• 
• Detail showing less than 1% ripple.
• 
• -----
• Additional details of the analysis, and example showing the design calculation, are [here (pdf file, 5 pages)](https://gofile.io/d/hMXWWc).

• What follows is a proposed concept of a simple (in principle!) way to generate a fixed-amplitude triangle wave, using two clocks, an XOR gate, and not using any processor cycles.
• It is practical in the low-mid-100-Hz ballpark, with typical mcu clocks. Motivating application is dither waveform for solenoid valve control signals.
• ----
• SUMMARY
• Two timers output two clocks A, B, with fixed 50% duty cycle. XOR(A,B) produces a symmetrical PWM triangle wave, with modulation frequency at ($f_{\rm A} + f_{\rm B})$ , and triangle frequency at $(f_{\rm A} - f_{\rm B})$. No other additional hardware. Illustrated below, showing how the XOR output is equivalent to a PWM. (click to zoom)
• [
• ](https://electrical.codidact.com/uploads/6bdrMJQBbLLbZvD8EJo2Fq1L)
• Given a master clock $f_{\rm CPU}$, the available frequencies are:
• $$f_{\rm TRIANGLE} = \frac{2 f_{\rm CPU}}{(n^2 - 1)}$$
• "$n$" should be an odd integer. The two clocks are set to $f_{\rm CPU}/(n+1)$ and $f_{\rm CPU}/(n-1)$, to make the dividers even numbers, so that A and B can have 50% duty cycles.
• The low-pass filter design is also parametrized by $n$. Let's define the passband at the triangle’s 5th harmonic, and the stopband at $(f_{ m A} + f_{ m B})$. The dimensionless value $f_{ m STOP} / f_{ m PASS}$ will represent the filter's transition band, and this value comes out to $n/5$.
• The dimensionless transition band corresponds to "filter complexity". A narrower transition band places more demands on the filter design. Given a lower limit of this value, a practical upper limit for the triangle frequency can then be derived as
• $$ \frac{f_{\rm TRIANGLE(max)}}{f_{\rm CPU}} = \frac{2}{25} \left(\frac{f_{\rm PASS}}{f_{\rm STOP}}\right)^2$$
• The table below uses this formula to show typical limits of the application:
• | min acceptable $f_{\rm STOP}/f_{\rm PASS}$ | max $f_{\rm TRIANGLE}/f_{\rm CPU}$ |
• |- | - |
• | 20 | 1 / 5000 |
• | 40 | 1 / 20000 |
• | 60 (shown in example) | 1 / 45000 |
• | 80 | 1 / 80000 |
• | 100 | 1 / 125000 |
• -----
• Example Circuit producing 199Hz from 10MHz f_cpu
• 
• Simulation of above circuit. 0-1V inputs produce 12mV - 988 mV peaks
• 
• Detail showing less than 1% ripple.
• 
• -----
• Additional details of the analysis, and example showing the design calculation, are [here (pdf file, 5 pages)](https://gofile.io/d/hMXWWc).

#19: Post edited by Pete W‭ · 2020-12-30T18:19:14Z (over 3 years ago)

Raw

Markdown

• What follows is a proposed concept of a simple (in principle!) way to generate a fixed-amplitude triangle wave, using two clocks, an XOR gate, and not using any processor cycles.
• It is practical in the low-mid-100-Hz ballpark, with typical mcu clocks. Motivating application is dither waveform for solenoid valve control signals.
• ----
• SUMMARY
• Two timers output two clocks A, B, with fixed 50% duty cycle. XOR(A,B) produces a symmetrical PWM triangle wave, with modulation frequency at ($f_{\rm A} + f_{\rm B})$ , and triangle frequency at $(f_{\rm A} - f_{\rm B})$. No other additional hardware. Illustrated below, showing how the XOR output is equivalent to a PWM. (click to zoom)
• [
• ](https://electrical.codidact.com/uploads/6bdrMJQBbLLbZvD8EJo2Fq1L)
• Given a master clock $f_{\rm CPU}$, the available frequencies are:
• $$f_{\rm TRIANGLE} = \frac{2 f_{\rm CPU}}{(n^2 - 1)}$$
• "$n$" should be an odd integer. The two clocks are set to $f_{\rm CPU}/(n+1)$ and $f_{\rm CPU}/(n-1)$, to make the dividers even numbers, so that A and B can have 50% duty cycles.
• The low-pass filter design is also parametrized by $n$. Let's define the passband at the triangle’s 5th harmonic, and the stopband at $(f_{ m A} + f_{ m B})$. The dimensionless value $f_{ m STOP} / f_{ m PASS}$ will represent the filter's transition band, and this value comes out to $n/5$.
• The dimensionless transition band corresponds to "filter complexity". A narrower transition band places more demands on the filter design. Given a lower limit of this value, a practical upper limit for the triangle frequency can then be derived as
• $$ \frac{f_{\rm TRIANGLE(max)}}{f_{\rm CPU}} = \frac{2}{25} \left(\frac{f_{\rm PASS}}{f_{\rm STOP}}\right)^2$$
• The table below uses this formula to show typical limits of the application:
• | min acceptable $f_{\rm STOP}/f_{\rm PASS}$ | max $f_{\rm TRIANGLE}/f_{\rm CPU}$ |
• |- | - |
• | 20 | 1 / 5000 |
• | 40 | 1 / 20000 |
• | 60 (shown in example) | 1 / 45000 |
• | 80 | 1 / 80000 |
• | 100 | 1 / 125000 |
• -----
• Example Circuit producing 199Hz from 10MHz f_cpu
• 
• Simulation of above circuit. 0-1V inputs produce 12mV - 988 mV peaks
• 
• Detail showing less than 1% ripple.
• 
• -----
• Additional details of the analysis, and example showing the design calculation, are [here (pdf file, 5 pages)](https://gofile.io/d/hMXWWc).

• What follows is a proposed concept of a simple (in principle!) way to generate a fixed-amplitude triangle wave, using two clocks, an XOR gate, and not using any processor cycles.
• It is practical in the low-mid-100-Hz ballpark, with typical mcu clocks. Motivating application is dither waveform for solenoid valve control signals.
• ----
• SUMMARY
• Two timers output two clocks A, B, with fixed 50% duty cycle. XOR(A,B) produces a symmetrical PWM triangle wave, with modulation frequency at ($f_{\rm A} + f_{\rm B})$ , and triangle frequency at $(f_{\rm A} - f_{\rm B})$. No other additional hardware. Illustrated below, showing how the XOR output is equivalent to a PWM. (click to zoom)
• [
• ](https://electrical.codidact.com/uploads/6bdrMJQBbLLbZvD8EJo2Fq1L)
• Given a master clock $f_{\rm CPU}$, the available frequencies are:
• $$f_{\rm TRIANGLE} = \frac{2 f_{\rm CPU}}{(n^2 - 1)}$$
• "$n$" should be an odd integer. The two clocks are set to $f_{\rm CPU}/(n+1)$ and $f_{\rm CPU}/(n-1)$, to make the dividers even numbers, so that A and B can have 50% duty cycles.
• The low-pass filter design, and the limitations that result from it, are also parametrized by $n$. Let's define the passband at the triangle’s 5th harmonic, and the stopband at $(f_{ m A} + f_{ m B})$. The dimensionless value $f_{ m STOP} / f_{ m PASS}$ will represent the filter's transition band, and this value comes out to $n/5$.
• The dimensionless transition band corresponds to "filter complexity". A narrower transition band places more demands on the filter design. Given a lower limit of this value, a practical upper limit for the triangle frequency can then be derived as
• $$ \frac{f_{\rm TRIANGLE(max)}}{f_{\rm CPU}} = \frac{2}{25} \left(\frac{f_{\rm PASS}}{f_{\rm STOP}}\right)^2$$
• The table below uses this formula to show typical limits of the application:
• | min acceptable $f_{\rm STOP}/f_{\rm PASS}$ | max $f_{\rm TRIANGLE}/f_{\rm CPU}$ |
• |- | - |
• | 20 | 1 / 5000 |
• | 40 | 1 / 20000 |
• | 60 (shown in example) | 1 / 45000 |
• | 80 | 1 / 80000 |
• | 100 | 1 / 125000 |
• -----
• Example Circuit producing 199Hz from 10MHz f_cpu
• 
• Simulation of above circuit. 0-1V inputs produce 12mV - 988 mV peaks
• 
• Detail showing less than 1% ripple.
• 
• -----
• Additional details of the analysis, and example showing the design calculation, are [here (pdf file, 5 pages)](https://gofile.io/d/hMXWWc).

#18: Post edited by Pete W‭ · 2020-12-30T18:09:50Z (over 3 years ago)

Raw

Markdown

• What follows is a proposed concept of a simple (in principle!) way to generate a fixed-amplitude triangle wave, using two clocks, an XOR gate, and not using any processor cycles.
• It is practical in the low-mid-100-Hz ballpark, with typical mcu clocks. Motivating application is dither waveform for solenoid valve control signals.
• ----
• SUMMARY
• Two timers output two clocks A, B, with fixed 50% duty cycle. XOR(A,B) produces a symmetrical PWM triangle wave, with modulation frequency at ($f_{\rm A} + f_{\rm B})$ , and triangle frequency at $(f_{\rm A} - f_{\rm B})$. No other additional hardware. Illustrated below, showing how the XOR output is equivalent to a PWM. (click to zoom)
• [
• ](https://electrical.codidact.com/uploads/6bdrMJQBbLLbZvD8EJo2Fq1L)
• Given a master clock $f_{ m CPU}$, the available triangle frequencies are:
• $$\frac{2 f_{ m CPU}}{(n^2 - 1)}$$
• $n$ should be an odd integer. The two clocks are set to $f_{ m CPU}/(n+1)$ and $f_{ m CPU}/(n-1)$, to make the dividers even numbers, so that A and B can have 50% duty cycles.
• The low-pass filter design is also parametrized by $n$. Let's define the passband at the triangle’s 5th harmonic, and the stopband at $(f_{\rm A} + f_{\rm B})$. The dimensionless value $f_{\rm STOP} / f_{\rm PASS}$ will represent the filter's transition band, and this value comes out to $n/5$.
• The dimensionless transition band corresponds to "filter complexity". A narrower transition band places more demands on the filter design. Given a lower limit of this value, a practical upper limit for the triangle frequency can then be derived as
• $$ \frac{f_{\rm TRIANGLE(max)}}{f_{\rm CPU}} = \frac{2}{25} \left(\frac{f_{\rm PASS}}{f_{\rm STOP}}\right)^2$$
• The table below uses this formula to show typical limits of the application:
• | min acceptable $f_{\rm STOP}/f_{\rm PASS}$ | max $f_{\rm TRIANGLE}/f_{\rm CPU}$ |
• |- | - |
• | 20 | 1 / 5000 |
• | 40 | 1 / 20000 |
• | 60 (shown in example) | 1 / 45000 |
• | 80 | 1 / 80000 |
• | 100 | 1 / 125000 |
• -----
• Example Circuit producing 199Hz from 10MHz f_cpu
• 
• Simulation of above circuit. 0-1V inputs produce 12mV - 988 mV peaks
• 
• Detail showing less than 1% ripple.
• 
• -----
• Additional details of the analysis, and example showing the design calculation, are [here (pdf file, 5 pages)](https://gofile.io/d/hMXWWc).

• What follows is a proposed concept of a simple (in principle!) way to generate a fixed-amplitude triangle wave, using two clocks, an XOR gate, and not using any processor cycles.
• It is practical in the low-mid-100-Hz ballpark, with typical mcu clocks. Motivating application is dither waveform for solenoid valve control signals.
• ----
• SUMMARY
• Two timers output two clocks A, B, with fixed 50% duty cycle. XOR(A,B) produces a symmetrical PWM triangle wave, with modulation frequency at ($f_{\rm A} + f_{\rm B})$ , and triangle frequency at $(f_{\rm A} - f_{\rm B})$. No other additional hardware. Illustrated below, showing how the XOR output is equivalent to a PWM. (click to zoom)
• [
• ](https://electrical.codidact.com/uploads/6bdrMJQBbLLbZvD8EJo2Fq1L)
• Given a master clock $f_{ m CPU}$, the available frequencies are:
• $$f_{\rm TRIANGLE} = \frac{2 f_{ m CPU}}{(n^2 - 1)}$$
• "$n$" should be an odd integer. The two clocks are set to $f_{ m CPU}/(n+1)$ and $f_{ m CPU}/(n-1)$, to make the dividers even numbers, so that A and B can have 50% duty cycles.
• The low-pass filter design is also parametrized by $n$. Let's define the passband at the triangle’s 5th harmonic, and the stopband at $(f_{\rm A} + f_{\rm B})$. The dimensionless value $f_{\rm STOP} / f_{\rm PASS}$ will represent the filter's transition band, and this value comes out to $n/5$.
• The dimensionless transition band corresponds to "filter complexity". A narrower transition band places more demands on the filter design. Given a lower limit of this value, a practical upper limit for the triangle frequency can then be derived as
• $$ \frac{f_{\rm TRIANGLE(max)}}{f_{\rm CPU}} = \frac{2}{25} \left(\frac{f_{\rm PASS}}{f_{\rm STOP}}\right)^2$$
• The table below uses this formula to show typical limits of the application:
• | min acceptable $f_{\rm STOP}/f_{\rm PASS}$ | max $f_{\rm TRIANGLE}/f_{\rm CPU}$ |
• |- | - |
• | 20 | 1 / 5000 |
• | 40 | 1 / 20000 |
• | 60 (shown in example) | 1 / 45000 |
• | 80 | 1 / 80000 |
• | 100 | 1 / 125000 |
• -----
• Example Circuit producing 199Hz from 10MHz f_cpu
• 
• Simulation of above circuit. 0-1V inputs produce 12mV - 988 mV peaks
• 
• Detail showing less than 1% ripple.
• 
• -----
• Additional details of the analysis, and example showing the design calculation, are [here (pdf file, 5 pages)](https://gofile.io/d/hMXWWc).

#17: Post edited by Pete W‭ · 2020-12-30T18:07:53Z (over 3 years ago)

Raw

Markdown

• What follows is a proposed concept of a simple (in principle!) way to generate a fixed-amplitude triangle wave, using two clocks, an XOR gate, and not using any processor cycles.
• It is practical in the low-mid-100-Hz ballpark, with typical mcu clocks. Motivating application is dither waveform for solenoid valve control signals.
• ----
• SUMMARY
• Two timers output two clocks A, B, with fixed 50% duty cycle. XOR(A,B) produces a symmetrical PWM triangle wave, with modulation frequency at ($f_{\rm A} + f_{\rm B})$ , and triangle frequency at $(f_{\rm A} - f_{\rm B})$. No other additional hardware. Illustrated below, showing how the XOR output is equivalent to a PWM. (click to zoom)
• [
• ](https://electrical.codidact.com/uploads/6bdrMJQBbLLbZvD8EJo2Fq1L)
• Given a master clock $f_{ m CPU}$, the available triangle frequencies are $2 f_{ m CPU} / (n^2 - 1)$, where $n$ is an odd integer. The two clocks are set to $f_{ m CPU}/(n+1)$ and $f_{ m CPU}/(n-1)$, to make the dividers even numbers, so that A and B can have 50% duty cycles.
• The low-pass filter design is also parametrized by $n$. Let's define the passband at the triangle’s 5th harmonic, and the stopband at $(f_{\rm A} + f_{\rm B})$. The dimensionless value $f_{\rm STOP} / f_{\rm PASS}$ will represent the filter's transition band, and this value comes out to $n/5$.
• The dimensionless transition band corresponds to "filter complexity". A narrower transition band places more demands on the filter design. Given a lower limit of this value, a practical upper limit for the triangle frequency can then be derived as
• $$ \frac{f_{\rm TRIANGLE(max)}}{f_{\rm CPU}} = \frac{2}{25} \left(\frac{f_{\rm PASS}}{f_{\rm STOP}}\right)^2$$
• The table below uses this formula to show typical limits of the application:
• | min acceptable $f_{\rm STOP}/f_{\rm PASS}$ | max $f_{\rm TRIANGLE}/f_{\rm CPU}$ |
• |- | - |
• | 20 | 1 / 5000 |
• | 40 | 1 / 20000 |
• | 60 (shown in example) | 1 / 45000 |
• | 80 | 1 / 80000 |
• | 100 | 1 / 125000 |
• -----
• Example Circuit producing 199Hz from 10MHz f_cpu
• 
• Simulation of above circuit. 0-1V inputs produce 12mV - 988 mV peaks
• 
• Detail showing less than 1% ripple.
• 
• -----
• Additional details of the analysis, and example showing the design calculation, are [here (pdf file, 5 pages)](https://gofile.io/d/hMXWWc).

• What follows is a proposed concept of a simple (in principle!) way to generate a fixed-amplitude triangle wave, using two clocks, an XOR gate, and not using any processor cycles.
• It is practical in the low-mid-100-Hz ballpark, with typical mcu clocks. Motivating application is dither waveform for solenoid valve control signals.
• ----
• SUMMARY
• Two timers output two clocks A, B, with fixed 50% duty cycle. XOR(A,B) produces a symmetrical PWM triangle wave, with modulation frequency at ($f_{\rm A} + f_{\rm B})$ , and triangle frequency at $(f_{\rm A} - f_{\rm B})$. No other additional hardware. Illustrated below, showing how the XOR output is equivalent to a PWM. (click to zoom)
• [
• ](https://electrical.codidact.com/uploads/6bdrMJQBbLLbZvD8EJo2Fq1L)
• Given a master clock $f_{ m CPU}$, the available triangle frequencies are:
• $$\frac{2 f_{ m CPU}}{(n^2 - 1)}$$
• $n$ should be an odd integer. The two clocks are set to $f_{ m CPU}/(n+1)$ and $f_{ m CPU}/(n-1)$, to make the dividers even numbers, so that A and B can have 50% duty cycles.
• The low-pass filter design is also parametrized by $n$. Let's define the passband at the triangle’s 5th harmonic, and the stopband at $(f_{\rm A} + f_{\rm B})$. The dimensionless value $f_{\rm STOP} / f_{\rm PASS}$ will represent the filter's transition band, and this value comes out to $n/5$.
• The dimensionless transition band corresponds to "filter complexity". A narrower transition band places more demands on the filter design. Given a lower limit of this value, a practical upper limit for the triangle frequency can then be derived as
• $$ \frac{f_{\rm TRIANGLE(max)}}{f_{\rm CPU}} = \frac{2}{25} \left(\frac{f_{\rm PASS}}{f_{\rm STOP}}\right)^2$$
• The table below uses this formula to show typical limits of the application:
• | min acceptable $f_{\rm STOP}/f_{\rm PASS}$ | max $f_{\rm TRIANGLE}/f_{\rm CPU}$ |
• |- | - |
• | 20 | 1 / 5000 |
• | 40 | 1 / 20000 |
• | 60 (shown in example) | 1 / 45000 |
• | 80 | 1 / 80000 |
• | 100 | 1 / 125000 |
• -----
• Example Circuit producing 199Hz from 10MHz f_cpu
• 
• Simulation of above circuit. 0-1V inputs produce 12mV - 988 mV peaks
• 
• Detail showing less than 1% ripple.
• 
• -----
• Additional details of the analysis, and example showing the design calculation, are [here (pdf file, 5 pages)](https://gofile.io/d/hMXWWc).

#16: Post edited by Pete W‭ · 2020-12-30T18:02:14Z (over 3 years ago)

Raw

Markdown

• What follows is a proposed concept of a simple (in principle!) way to generate a fixed-amplitude triangle wave, using two clocks, an XOR gate, and not using any processor cycles.
• It is practical in the low-mid-100-Hz ballpark, with typical mcu clocks. Motivating application is dither waveform for solenoid valve control signals.
• ----
• SUMMARY
• Two timers output two clocks A, B, with fixed 50% duty cycle. XOR(A,B) produces a symmetrical PWM triangle wave, with modulation frequency at ($f_{\rm A} + f_{\rm B})$ , and triangle frequency at $(f_{\rm A} - f_{\rm B})$. No other additional hardware. Illustrated below, showing how the XOR output is equivalent to a PWM. (click to zoom)
• [
• ](https://electrical.codidact.com/uploads/6bdrMJQBbLLbZvD8EJo2Fq1L)
• Given a master clock $f_{\rm CPU}$, the available triangle frequencies are $2 f_{\rm CPU} / (n^2 - 1)$, where $n$ is an odd integer. The two clocks are set to $f_{\rm CPU}/(n+1)$ and $f_{\rm CPU}/(n-1)$, to make the dividers even numbers, so that A and B can have 50% duty cycles.
• The low-pass filter design is also parametrized by $n$. Let's define the passband at the triangle’s 5th harmonic, and the stopband at $(f_{\rm A} + f_{\rm B})$. The dimensionless value $f_{\rm STOP} / f_{\rm PASS}$ will represent the filter's transition band, and this value comes out to $n/5$.
• The dimensionless transition band corresponds to "filter complexity". A narrower transition band places more demands on the filter design. Given a lower limit of this value, the practical upper limit for the triangle frequency can then be derived as
• $$ \frac{f_{\rm TRIANGLE(max)}}{f_{\rm CPU}} = \frac{2}{25} \left(\frac{f_{\rm PASS}}{f_{\rm STOP}}\right)^2$$
• The table below uses this formula to show typical limits of the application:
• | min acceptable $f_{\rm STOP}/f_{\rm PASS}$ | max $f_{\rm TRIANGLE}/f_{\rm CPU}$ |
• |- | - |
• | 20 | 1 / 5000 |
• | 40 | 1 / 20000 |
• | 60 (shown in example) | 1 / 45000 |
• | 80 | 1 / 80000 |
• | 100 | 1 / 125000 |
• -----
• Example Circuit producing 199Hz from 10MHz f_cpu
• 
• Simulation of above circuit. 0-1V inputs produce 12mV - 988 mV peaks
• 
• Detail showing less than 1% ripple.
• 
• -----
• Additional details of the analysis, and example showing the design calculation, are [here (pdf file, 5 pages)](https://gofile.io/d/hMXWWc).

• What follows is a proposed concept of a simple (in principle!) way to generate a fixed-amplitude triangle wave, using two clocks, an XOR gate, and not using any processor cycles.
• It is practical in the low-mid-100-Hz ballpark, with typical mcu clocks. Motivating application is dither waveform for solenoid valve control signals.
• ----
• SUMMARY
• Two timers output two clocks A, B, with fixed 50% duty cycle. XOR(A,B) produces a symmetrical PWM triangle wave, with modulation frequency at ($f_{\rm A} + f_{\rm B})$ , and triangle frequency at $(f_{\rm A} - f_{\rm B})$. No other additional hardware. Illustrated below, showing how the XOR output is equivalent to a PWM. (click to zoom)
• [
• ](https://electrical.codidact.com/uploads/6bdrMJQBbLLbZvD8EJo2Fq1L)
• Given a master clock $f_{\rm CPU}$, the available triangle frequencies are $2 f_{\rm CPU} / (n^2 - 1)$, where $n$ is an odd integer. The two clocks are set to $f_{\rm CPU}/(n+1)$ and $f_{\rm CPU}/(n-1)$, to make the dividers even numbers, so that A and B can have 50% duty cycles.
• The low-pass filter design is also parametrized by $n$. Let's define the passband at the triangle’s 5th harmonic, and the stopband at $(f_{\rm A} + f_{\rm B})$. The dimensionless value $f_{\rm STOP} / f_{\rm PASS}$ will represent the filter's transition band, and this value comes out to $n/5$.
• The dimensionless transition band corresponds to "filter complexity". A narrower transition band places more demands on the filter design. Given a lower limit of this value, a practical upper limit for the triangle frequency can then be derived as
• $$ \frac{f_{\rm TRIANGLE(max)}}{f_{\rm CPU}} = \frac{2}{25} \left(\frac{f_{\rm PASS}}{f_{\rm STOP}}\right)^2$$
• The table below uses this formula to show typical limits of the application:
• | min acceptable $f_{\rm STOP}/f_{\rm PASS}$ | max $f_{\rm TRIANGLE}/f_{\rm CPU}$ |
• |- | - |
• | 20 | 1 / 5000 |
• | 40 | 1 / 20000 |
• | 60 (shown in example) | 1 / 45000 |
• | 80 | 1 / 80000 |
• | 100 | 1 / 125000 |
• -----
• Example Circuit producing 199Hz from 10MHz f_cpu
• 
• Simulation of above circuit. 0-1V inputs produce 12mV - 988 mV peaks
• 
• Detail showing less than 1% ripple.
• 
• -----
• Additional details of the analysis, and example showing the design calculation, are [here (pdf file, 5 pages)](https://gofile.io/d/hMXWWc).

#15: Post edited by Pete W‭ · 2020-12-30T18:00:51Z (over 3 years ago)

Raw

Markdown

• What follows is a proposed concept of a simple (in principle!) way to generate a fixed-amplitude triangle wave, using two clocks, an XOR gate, and not using any processor cycles.
• It is practical in the low-mid-100-Hz ballpark, with typical mcu clocks. Motivating application is dither waveform for solenoid valve control signals.
• ----
• SUMMARY
• Two timers output two clocks A, B, with fixed 50% duty cycle. XOR(A,B) produces a symmetrical PWM triangle wave, with modulation frequency at ($f_{\rm A} + f_{\rm B})$ , and triangle frequency at $(f_{\rm A} - f_{\rm B})$. No other additional hardware. Illustrated below, showing how the XOR output is equivalent to a PWM. (click to zoom)
• [
• ](https://electrical.codidact.com/uploads/6bdrMJQBbLLbZvD8EJo2Fq1L)
• Given a master clock $f_{\rm CPU}$, the available triangle frequencies are $2 f_{\rm CPU} / (n^2 - 1)$, where $n$ is an odd integer. The two clocks are set to $f_{\rm CPU}/(n+1)$ and $f_{\rm CPU}/(n-1)$, to make the dividers even numbers, so that A and B can have 50% duty cycles.
• The low-pass filter design is also parametrized by $n$. If we define passband at the triangle’s 5th harmonic, and the stopband at $(f_{ m A} + f_{ m B})$, then dimensionless value $f_{ m STOP} / f_{ m PASS}$, representing the filter's transition band, comes out to $n/5$.
• The dimensionless transition band corresponds to "filter complexity". A narrower transition band places more demands on the filter design. Given a lower limit of this value, the practical upper limit for the triangle frequency can then be derived as
• $$ \frac{f_{\rm TRIANGLE(max)}}{f_{\rm CPU}} = \frac{2}{25} \left(\frac{f_{\rm PASS}}{f_{\rm STOP}}\right)^2$$
• The table below uses this formula to show typical limits of the application:
• | min acceptable $f_{\rm STOP}/f_{\rm PASS}$ | max $f_{\rm TRIANGLE}/f_{\rm CPU}$ |
• |- | - |
• | 20 | 1 / 5000 |
• | 40 | 1 / 20000 |
• | 60 (shown in example) | 1 / 45000 |
• | 80 | 1 / 80000 |
• | 100 | 1 / 125000 |
• -----
• Example Circuit producing 199Hz from 10MHz f_cpu
• 
• Simulation of above circuit. 0-1V inputs produce 12mV - 988 mV peaks
• 
• Detail showing less than 1% ripple.
• 
• -----
• Additional details of the analysis, and example showing the design calculation, are [here (pdf file, 5 pages)](https://gofile.io/d/hMXWWc).

• What follows is a proposed concept of a simple (in principle!) way to generate a fixed-amplitude triangle wave, using two clocks, an XOR gate, and not using any processor cycles.
• It is practical in the low-mid-100-Hz ballpark, with typical mcu clocks. Motivating application is dither waveform for solenoid valve control signals.
• ----
• SUMMARY
• Two timers output two clocks A, B, with fixed 50% duty cycle. XOR(A,B) produces a symmetrical PWM triangle wave, with modulation frequency at ($f_{\rm A} + f_{\rm B})$ , and triangle frequency at $(f_{\rm A} - f_{\rm B})$. No other additional hardware. Illustrated below, showing how the XOR output is equivalent to a PWM. (click to zoom)
• [
• ](https://electrical.codidact.com/uploads/6bdrMJQBbLLbZvD8EJo2Fq1L)
• Given a master clock $f_{\rm CPU}$, the available triangle frequencies are $2 f_{\rm CPU} / (n^2 - 1)$, where $n$ is an odd integer. The two clocks are set to $f_{\rm CPU}/(n+1)$ and $f_{\rm CPU}/(n-1)$, to make the dividers even numbers, so that A and B can have 50% duty cycles.
• The low-pass filter design is also parametrized by $n$. Let's define the passband at the triangle’s 5th harmonic, and the stopband at $(f_{ m A} + f_{ m B})$. The dimensionless value $f_{ m STOP} / f_{ m PASS}$ will represent the filter's transition band, and this value comes out to $n/5$.
• The dimensionless transition band corresponds to "filter complexity". A narrower transition band places more demands on the filter design. Given a lower limit of this value, the practical upper limit for the triangle frequency can then be derived as
• $$ \frac{f_{\rm TRIANGLE(max)}}{f_{\rm CPU}} = \frac{2}{25} \left(\frac{f_{\rm PASS}}{f_{\rm STOP}}\right)^2$$
• The table below uses this formula to show typical limits of the application:
• | min acceptable $f_{\rm STOP}/f_{\rm PASS}$ | max $f_{\rm TRIANGLE}/f_{\rm CPU}$ |
• |- | - |
• | 20 | 1 / 5000 |
• | 40 | 1 / 20000 |
• | 60 (shown in example) | 1 / 45000 |
• | 80 | 1 / 80000 |
• | 100 | 1 / 125000 |
• -----
• Example Circuit producing 199Hz from 10MHz f_cpu
• 
• Simulation of above circuit. 0-1V inputs produce 12mV - 988 mV peaks
• 
• Detail showing less than 1% ripple.
• 
• -----
• Additional details of the analysis, and example showing the design calculation, are [here (pdf file, 5 pages)](https://gofile.io/d/hMXWWc).

#14: Post edited by Pete W‭ · 2020-12-30T17:59:08Z (over 3 years ago)

Raw

Markdown

• What follows is a proposed concept of a simple (in principle!) way to generate a fixed-amplitude triangle wave, using two clocks, an XOR gate, and not using any processor cycles.
• It is practical in the low-mid-100-Hz ballpark, with typical mcu clocks. Motivating application is dither waveform for solenoid valve control signals.
• ----
• SUMMARY
• Two timers output two clocks A, B, with fixed 50% duty cycle. XOR(A,B) produces a symmetrical PWM triangle wave, with modulation frequency at ($f_{\rm A} + f_{\rm B})$ , and triangle frequency at $(f_{\rm A} - f_{\rm B})$. No other additional hardware. Illustrated below, showing how the XOR output is equivalent to a PWM. (click to zoom)
• [
• ](https://electrical.codidact.com/uploads/6bdrMJQBbLLbZvD8EJo2Fq1L)
• Given a master clock $f_{\rm CPU}$, the available triangle frequencies are $2 f_{\rm CPU} / (n^2 - 1)$, where $n$ is an odd integer. The two clocks are set to $f_{\rm CPU}/(n+1)$ and $f_{\rm CPU}/(n-1)$, to make the dividers even numbers, so that A and B can have 50% duty cycles.
• The low-pass filter design is also parametrized by $n$. If we define passband at the triangle’s 5th harmonic, and the stopband at $(f_{ m A} + f_{ m B})$, then non dimensional value $f_{ m STOP} / f_{ m PASS}$, representing the filter's transition band, comes out to $n/5$.
• The non dimensional transition band corresponds to "filter complexity". A narrower transition band places more demands on the filter design. Given a lower limit of this value, the practical upper limit for the triangle frequency can then be derived as
• $$ \frac{f_{\rm TRIANGLE(max)}}{f_{\rm CPU}} = \frac{2}{25} \left(\frac{f_{\rm PASS}}{f_{\rm STOP}}\right)^2$$
• The table below uses this formula to show typical limits of the application:
• | min acceptable $f_{\rm STOP}/f_{\rm PASS}$ | max $f_{\rm TRIANGLE}/f_{\rm CPU}$ |
• |- | - |
• | 20 | 1 / 5000 |
• | 40 | 1 / 20000 |
• | 60 (shown in example) | 1 / 45000 |
• | 80 | 1 / 80000 |
• | 100 | 1 / 125000 |
• -----
• Example Circuit producing 199Hz from 10MHz f_cpu
• 
• Simulation of above circuit. 0-1V inputs produce 12mV - 988 mV peaks
• 
• Detail showing less than 1% ripple.
• 
• -----
• Additional details of the analysis, and example showing the design calculation, are [here (pdf file, 5 pages)](https://gofile.io/d/hMXWWc).

• What follows is a proposed concept of a simple (in principle!) way to generate a fixed-amplitude triangle wave, using two clocks, an XOR gate, and not using any processor cycles.
• It is practical in the low-mid-100-Hz ballpark, with typical mcu clocks. Motivating application is dither waveform for solenoid valve control signals.
• ----
• SUMMARY
• Two timers output two clocks A, B, with fixed 50% duty cycle. XOR(A,B) produces a symmetrical PWM triangle wave, with modulation frequency at ($f_{\rm A} + f_{\rm B})$ , and triangle frequency at $(f_{\rm A} - f_{\rm B})$. No other additional hardware. Illustrated below, showing how the XOR output is equivalent to a PWM. (click to zoom)
• [
• ](https://electrical.codidact.com/uploads/6bdrMJQBbLLbZvD8EJo2Fq1L)
• Given a master clock $f_{\rm CPU}$, the available triangle frequencies are $2 f_{\rm CPU} / (n^2 - 1)$, where $n$ is an odd integer. The two clocks are set to $f_{\rm CPU}/(n+1)$ and $f_{\rm CPU}/(n-1)$, to make the dividers even numbers, so that A and B can have 50% duty cycles.
• The low-pass filter design is also parametrized by $n$. If we define passband at the triangle’s 5th harmonic, and the stopband at $(f_{ m A} + f_{ m B})$, then dimensionless value $f_{ m STOP} / f_{ m PASS}$, representing the filter's transition band, comes out to $n/5$.
• The dimensionless transition band corresponds to "filter complexity". A narrower transition band places more demands on the filter design. Given a lower limit of this value, the practical upper limit for the triangle frequency can then be derived as
• $$ \frac{f_{\rm TRIANGLE(max)}}{f_{\rm CPU}} = \frac{2}{25} \left(\frac{f_{\rm PASS}}{f_{\rm STOP}}\right)^2$$
• The table below uses this formula to show typical limits of the application:
• | min acceptable $f_{\rm STOP}/f_{\rm PASS}$ | max $f_{\rm TRIANGLE}/f_{\rm CPU}$ |
• |- | - |
• | 20 | 1 / 5000 |
• | 40 | 1 / 20000 |
• | 60 (shown in example) | 1 / 45000 |
• | 80 | 1 / 80000 |
• | 100 | 1 / 125000 |
• -----
• Example Circuit producing 199Hz from 10MHz f_cpu
• 
• Simulation of above circuit. 0-1V inputs produce 12mV - 988 mV peaks
• 
• Detail showing less than 1% ripple.
• 
• -----
• Additional details of the analysis, and example showing the design calculation, are [here (pdf file, 5 pages)](https://gofile.io/d/hMXWWc).

#13: Post edited by Pete W‭ · 2020-12-30T17:57:54Z (over 3 years ago)

Raw

Markdown

• What follows is a proposed concept of a simple (in principle!) way to generate a fixed-amplitude triangle wave, using two clocks, an XOR gate, and not using any processor cycles.
• It is practical in the low-mid-100-Hz ballpark, with typical mcu clocks. Motivating application is dither waveform for solenoid valve control signals.
• ----
• SUMMARY
• Two timers output two clocks A, B, with fixed 50% duty cycle. XOR(A,B) produces a symmetrical PWM triangle wave, with modulation frequency at ($f_{\rm A} + f_{\rm B})$ , and triangle frequency at $(f_{\rm A} - f_{\rm B})$. No other additional hardware. Illustrated below, showing how the XOR output is equivalent to a PWM. (click to zoom)
• [
• ](https://electrical.codidact.com/uploads/6bdrMJQBbLLbZvD8EJo2Fq1L)
• Given a master clock $f_{\rm CPU}$, the available triangle frequencies are $2 f_{\rm CPU} / (n^2 - 1)$, where $n$ is an odd integer. The two clocks are set to $f_{\rm CPU}/(n+1)$ and $f_{\rm CPU}/(n-1)$, to make the dividers even numbers, so that A and B can have 50% duty cycles.
• The low-pass filter design is also parametrized by $n$. If we define passband at the triangle’s 5th harmonic, and the stopband at $(f_{ m A} + f_{ m B})$, then non dimensional value $f_{ m STOP} / f_{ m PASS}$, representing the transition band, comes out to $n/5$.
• The non dimensional transition band corresponds to "filter complexity". A narrower transition band places more demands on the filter design. Given a lower limit of this value, the practical upper limit for the triangle frequency can then be derived as
• $$ \frac{f_{\rm TRIANGLE(max)}}{f_{\rm CPU}} = \frac{2}{25} \left(\frac{f_{\rm PASS}}{f_{\rm STOP}}\right)^2$$
• The table below uses this formula to show typical limits of the application:
• | min acceptable $f_{\rm STOP}/f_{\rm PASS}$ | max $f_{\rm TRIANGLE}/f_{\rm CPU}$ |
• |- | - |
• | 20 | 1 / 5000 |
• | 40 | 1 / 20000 |
• | 60 (shown in example) | 1 / 45000 |
• | 80 | 1 / 80000 |
• | 100 | 1 / 125000 |
• -----
• Example Circuit producing 199Hz from 10MHz f_cpu
• 
• Simulation of above circuit. 0-1V inputs produce 12mV - 988 mV peaks
• 
• Detail showing less than 1% ripple.
• 
• -----
• Additional details of the analysis, and example showing the design calculation, are [here (pdf file, 5 pages)](https://gofile.io/d/hMXWWc).

• What follows is a proposed concept of a simple (in principle!) way to generate a fixed-amplitude triangle wave, using two clocks, an XOR gate, and not using any processor cycles.
• It is practical in the low-mid-100-Hz ballpark, with typical mcu clocks. Motivating application is dither waveform for solenoid valve control signals.
• ----
• SUMMARY
• Two timers output two clocks A, B, with fixed 50% duty cycle. XOR(A,B) produces a symmetrical PWM triangle wave, with modulation frequency at ($f_{\rm A} + f_{\rm B})$ , and triangle frequency at $(f_{\rm A} - f_{\rm B})$. No other additional hardware. Illustrated below, showing how the XOR output is equivalent to a PWM. (click to zoom)
• [
• ](https://electrical.codidact.com/uploads/6bdrMJQBbLLbZvD8EJo2Fq1L)
• Given a master clock $f_{\rm CPU}$, the available triangle frequencies are $2 f_{\rm CPU} / (n^2 - 1)$, where $n$ is an odd integer. The two clocks are set to $f_{\rm CPU}/(n+1)$ and $f_{\rm CPU}/(n-1)$, to make the dividers even numbers, so that A and B can have 50% duty cycles.
• The low-pass filter design is also parametrized by $n$. If we define passband at the triangle’s 5th harmonic, and the stopband at $(f_{ m A} + f_{ m B})$, then non dimensional value $f_{ m STOP} / f_{ m PASS}$, representing the filter's transition band, comes out to $n/5$.
• The non dimensional transition band corresponds to "filter complexity". A narrower transition band places more demands on the filter design. Given a lower limit of this value, the practical upper limit for the triangle frequency can then be derived as
• $$ \frac{f_{\rm TRIANGLE(max)}}{f_{\rm CPU}} = \frac{2}{25} \left(\frac{f_{\rm PASS}}{f_{\rm STOP}}\right)^2$$
• The table below uses this formula to show typical limits of the application:
• | min acceptable $f_{\rm STOP}/f_{\rm PASS}$ | max $f_{\rm TRIANGLE}/f_{\rm CPU}$ |
• |- | - |
• | 20 | 1 / 5000 |
• | 40 | 1 / 20000 |
• | 60 (shown in example) | 1 / 45000 |
• | 80 | 1 / 80000 |
• | 100 | 1 / 125000 |
• -----
• Example Circuit producing 199Hz from 10MHz f_cpu
• 
• Simulation of above circuit. 0-1V inputs produce 12mV - 988 mV peaks
• 
• Detail showing less than 1% ripple.
• 
• -----
• Additional details of the analysis, and example showing the design calculation, are [here (pdf file, 5 pages)](https://gofile.io/d/hMXWWc).

#12: Post edited by Pete W‭ · 2020-12-30T17:55:53Z (over 3 years ago)

Raw

Markdown

• What follows is a proposed concept of a simple (in principle!) way to generate a fixed-amplitude triangle wave, using two clocks, an XOR gate, and not using any processor cycles.
• It is practical in the low-mid-100-Hz ballpark, with typical mcu clocks. Motivating application is dither waveform for solenoid valve control signals.
• ----
• SUMMARY
• Two timers output two clocks A, B, with fixed 50% duty cycle. XOR(A,B) produces a symmetrical PWM triangle wave, with modulation frequency at ($f_{\rm A} + f_{\rm B})$ , and triangle frequency at $(f_{\rm A} - f_{\rm B})$. No other additional hardware. Illustrated below, showing how the XOR output is equivalent to a PWM. (click to zoom)
• [
• ](https://electrical.codidact.com/uploads/6bdrMJQBbLLbZvD8EJo2Fq1L)
• Given a master clock $f_{\rm CPU}$, the available triangle frequencies are $2 f_{\rm CPU} / (n^2 - 1)$, where $n$ is an odd integer. The two clocks are set to $f_{\rm CPU}/(n+1)$ and $f_{\rm CPU}/(n-1)$, to make the dividers even numbers, so that A and B can have 50% duty cycles.
• The low-pass filter design is also parametrized by $n$. If we define passband at the triangle’s 5th harmonic, then non dimensional value $f_{ m STOP} / f_{ m PASS}$, representing the transition band, comes out to $n/5$.
• The non dimensional transition band corresponds to "filter complexity". A narrower transition band places more demands on the filter design. Given a lower limit of this value, the practical upper limit for the triangle frequency can then be derived as
• $$ \frac{f_{\rm TRIANGLE(max)}}{f_{\rm CPU}} = \frac{2}{25} \left(\frac{f_{\rm PASS}}{f_{\rm STOP}}\right)^2$$
• The table below uses this formula to show typical limits of the application:
• | min acceptable $f_{\rm STOP}/f_{\rm PASS}$ | max $f_{\rm TRIANGLE}/f_{\rm CPU}$ |
• |- | - |
• | 20 | 1 / 5000 |
• | 40 | 1 / 20000 |
• | 60 (shown in example) | 1 / 45000 |
• | 80 | 1 / 80000 |
• | 100 | 1 / 125000 |
• -----
• Example Circuit producing 199Hz from 10MHz f_cpu
• 
• Simulation of above circuit. 0-1V inputs produce 12mV - 988 mV peaks
• 
• Detail showing less than 1% ripple.
• 
• -----
• Additional details of the analysis, and example showing the design calculation, are [here (pdf file, 5 pages)](https://gofile.io/d/hMXWWc).

• What follows is a proposed concept of a simple (in principle!) way to generate a fixed-amplitude triangle wave, using two clocks, an XOR gate, and not using any processor cycles.
• It is practical in the low-mid-100-Hz ballpark, with typical mcu clocks. Motivating application is dither waveform for solenoid valve control signals.
• ----
• SUMMARY
• Two timers output two clocks A, B, with fixed 50% duty cycle. XOR(A,B) produces a symmetrical PWM triangle wave, with modulation frequency at ($f_{\rm A} + f_{\rm B})$ , and triangle frequency at $(f_{\rm A} - f_{\rm B})$. No other additional hardware. Illustrated below, showing how the XOR output is equivalent to a PWM. (click to zoom)
• [
• ](https://electrical.codidact.com/uploads/6bdrMJQBbLLbZvD8EJo2Fq1L)
• Given a master clock $f_{\rm CPU}$, the available triangle frequencies are $2 f_{\rm CPU} / (n^2 - 1)$, where $n$ is an odd integer. The two clocks are set to $f_{\rm CPU}/(n+1)$ and $f_{\rm CPU}/(n-1)$, to make the dividers even numbers, so that A and B can have 50% duty cycles.
• The low-pass filter design is also parametrized by $n$. If we define passband at the triangle’s 5th harmonic, and the stopband at $(f_{\rm A} + f_{\rm B})$, then non dimensional value $f_{ m STOP} / f_{ m PASS}$, representing the transition band, comes out to $n/5$.
• The non dimensional transition band corresponds to "filter complexity". A narrower transition band places more demands on the filter design. Given a lower limit of this value, the practical upper limit for the triangle frequency can then be derived as
• $$ \frac{f_{\rm TRIANGLE(max)}}{f_{\rm CPU}} = \frac{2}{25} \left(\frac{f_{\rm PASS}}{f_{\rm STOP}}\right)^2$$
• The table below uses this formula to show typical limits of the application:
• | min acceptable $f_{\rm STOP}/f_{\rm PASS}$ | max $f_{\rm TRIANGLE}/f_{\rm CPU}$ |
• |- | - |
• | 20 | 1 / 5000 |
• | 40 | 1 / 20000 |
• | 60 (shown in example) | 1 / 45000 |
• | 80 | 1 / 80000 |
• | 100 | 1 / 125000 |
• -----
• Example Circuit producing 199Hz from 10MHz f_cpu
• 
• Simulation of above circuit. 0-1V inputs produce 12mV - 988 mV peaks
• 
• Detail showing less than 1% ripple.
• 
• -----
• Additional details of the analysis, and example showing the design calculation, are [here (pdf file, 5 pages)](https://gofile.io/d/hMXWWc).

#11: Post edited by Pete W‭ · 2020-12-30T17:53:45Z (over 3 years ago)

Raw

Markdown

• What follows is a proposed concept of a simple (in principle!) way to generate a fixed-amplitude triangle wave, using two clocks, an XOR gate, and not using any processor cycles.
• It is practical in the low-mid-100-Hz ballpark, with typical mcu clocks. Motivating application is dither waveform for solenoid valve control signals.
• ----
• SUMMARY
• Two timers output two clocks A, B, with fixed 50% duty cycle. XOR(A,B) produces a symmetrical PWM triangle wave, with modulation frequency at ($f_{\rm A} + f_{\rm B})$ , and triangle frequency at $(f_{\rm A} - f_{\rm B})$. No other additional hardware. Illustrated below, showing how the XOR output is equivalent to a PWM. (click to zoom)
• [
• ](https://electrical.codidact.com/uploads/6bdrMJQBbLLbZvD8EJo2Fq1L)
• Given a master clock $f_{ m CPU}$, the available triangle frequencies are $2 f_{ m CPU} / (n^2 - 1)$, where $n$ is an odd integer. The two clocks are set to $f_{ m CPU}/(n+1)$ and $f_{ m CPU}/(n-1)$, to make the dividers even numbers (to allow 50% duty cycles on A and B).
• The low-pass filter design is also parametrized by $n$. If we define passband at the triangle’s 5th harmonic, then non dimensional value $f_{\rm STOP} / f_{\rm PASS}$, representing the transition band, comes out to $n/5$.
• The non dimensional transition band corresponds to "filter complexity". A narrower transition band places more demands on the filter design. Given a lower limit of this value, the practical upper limit for the triangle frequency can then be derived as
• $$ \frac{f_{\rm TRIANGLE(max)}}{f_{\rm CPU}} = \frac{2}{25} \left(\frac{f_{\rm PASS}}{f_{\rm STOP}}\right)^2$$
• The table below uses this formula to show typical limits of the application:
• | min acceptable $f_{\rm STOP}/f_{\rm PASS}$ | max $f_{\rm TRIANGLE}/f_{\rm CPU}$ |
• |- | - |
• | 20 | 1 / 5000 |
• | 40 | 1 / 20000 |
• | 60 (shown in example) | 1 / 45000 |
• | 80 | 1 / 80000 |
• | 100 | 1 / 125000 |
• -----
• Example Circuit producing 199Hz from 10MHz f_cpu
• 
• Simulation of above circuit. 0-1V inputs produce 12mV - 988 mV peaks
• 
• Detail showing less than 1% ripple.
• 
• -----
• Additional details of the analysis, and example showing the design calculation, are [here (pdf file, 5 pages)](https://gofile.io/d/hMXWWc).

• What follows is a proposed concept of a simple (in principle!) way to generate a fixed-amplitude triangle wave, using two clocks, an XOR gate, and not using any processor cycles.
• It is practical in the low-mid-100-Hz ballpark, with typical mcu clocks. Motivating application is dither waveform for solenoid valve control signals.
• ----
• SUMMARY
• Two timers output two clocks A, B, with fixed 50% duty cycle. XOR(A,B) produces a symmetrical PWM triangle wave, with modulation frequency at ($f_{\rm A} + f_{\rm B})$ , and triangle frequency at $(f_{\rm A} - f_{\rm B})$. No other additional hardware. Illustrated below, showing how the XOR output is equivalent to a PWM. (click to zoom)
• [
• ](https://electrical.codidact.com/uploads/6bdrMJQBbLLbZvD8EJo2Fq1L)
• Given a master clock $f_{ m CPU}$, the available triangle frequencies are $2 f_{ m CPU} / (n^2 - 1)$, where $n$ is an odd integer. The two clocks are set to $f_{ m CPU}/(n+1)$ and $f_{ m CPU}/(n-1)$, to make the dividers even numbers, so that A and B can have 50% duty cycles.
• The low-pass filter design is also parametrized by $n$. If we define passband at the triangle’s 5th harmonic, then non dimensional value $f_{\rm STOP} / f_{\rm PASS}$, representing the transition band, comes out to $n/5$.
• The non dimensional transition band corresponds to "filter complexity". A narrower transition band places more demands on the filter design. Given a lower limit of this value, the practical upper limit for the triangle frequency can then be derived as
• $$ \frac{f_{\rm TRIANGLE(max)}}{f_{\rm CPU}} = \frac{2}{25} \left(\frac{f_{\rm PASS}}{f_{\rm STOP}}\right)^2$$
• The table below uses this formula to show typical limits of the application:
• | min acceptable $f_{\rm STOP}/f_{\rm PASS}$ | max $f_{\rm TRIANGLE}/f_{\rm CPU}$ |
• |- | - |
• | 20 | 1 / 5000 |
• | 40 | 1 / 20000 |
• | 60 (shown in example) | 1 / 45000 |
• | 80 | 1 / 80000 |
• | 100 | 1 / 125000 |
• -----
• Example Circuit producing 199Hz from 10MHz f_cpu
• 
• Simulation of above circuit. 0-1V inputs produce 12mV - 988 mV peaks
• 
• Detail showing less than 1% ripple.
• 
• -----
• Additional details of the analysis, and example showing the design calculation, are [here (pdf file, 5 pages)](https://gofile.io/d/hMXWWc).

#10: Post edited by Pete W‭ · 2020-12-30T17:53:17Z (over 3 years ago)

Raw

Markdown

• What follows is a proposed concept of a simple (in principle!) way to generate a fixed-amplitude triangle wave, using two clocks, an XOR gate, and not using any processor cycles.
• It is practical in the low-mid-100-Hz ballpark, with typical mcu clocks. Motivating application is dither waveform for solenoid valve control signals.
• ----
• SUMMARY
• Two timers output two clocks A, B, with fixed 50% duty cycle. XOR(A,B) produces a symmetrical PWM triangle wave, with modulation frequency at ($f_{\rm A} + f_{\rm B})$ , and triangle frequency at $(f_{\rm A} - f_{\rm B})$. No other additional hardware. Illustrated below, showing how the XOR output is equivalent to a PWM. (click to zoom)
• [
• ](https://electrical.codidact.com/uploads/6bdrMJQBbLLbZvD8EJo2Fq1L)
• Given a master clock $f_{ m CPU}$, the available triangle frequencies are $2 f_{ m CPU} / (n^2 - 1)$, where $n$ is an odd integer. The two clocks are set to $f_{ m CPU}/(n+1)$ and $f_{ m CPU}/(n-1)$, to make the dividers even numbers (to allow 50% duty cycle).
• The low-pass filter design is also parametrized by $n$. If we define passband at the triangle’s 5th harmonic, then non dimensional value $f_{\rm STOP} / f_{\rm PASS}$, representing the transition band, comes out to $n/5$.
• The non dimensional transition band corresponds to "filter complexity". A narrower transition band places more demands on the filter design. Given a lower limit of this value, the practical upper limit for the triangle frequency can then be derived as
• $$ \frac{f_{\rm TRIANGLE(max)}}{f_{\rm CPU}} = \frac{2}{25} \left(\frac{f_{\rm PASS}}{f_{\rm STOP}}\right)^2$$
• The table below uses this formula to show typical limits of the application:
• | min acceptable $f_{\rm STOP}/f_{\rm PASS}$ | max $f_{\rm TRIANGLE}/f_{\rm CPU}$ |
• |- | - |
• | 20 | 1 / 5000 |
• | 40 | 1 / 20000 |
• | 60 (shown in example) | 1 / 45000 |
• | 80 | 1 / 80000 |
• | 100 | 1 / 125000 |
• -----
• Example Circuit producing 199Hz from 10MHz f_cpu
• 
• Simulation of above circuit. 0-1V inputs produce 12mV - 988 mV peaks
• 
• Detail showing less than 1% ripple.
• 
• -----
• Additional details of the analysis, and example showing the design calculation, are [here (pdf file, 5 pages)](https://gofile.io/d/hMXWWc).

• What follows is a proposed concept of a simple (in principle!) way to generate a fixed-amplitude triangle wave, using two clocks, an XOR gate, and not using any processor cycles.
• It is practical in the low-mid-100-Hz ballpark, with typical mcu clocks. Motivating application is dither waveform for solenoid valve control signals.
• ----
• SUMMARY
• Two timers output two clocks A, B, with fixed 50% duty cycle. XOR(A,B) produces a symmetrical PWM triangle wave, with modulation frequency at ($f_{\rm A} + f_{\rm B})$ , and triangle frequency at $(f_{\rm A} - f_{\rm B})$. No other additional hardware. Illustrated below, showing how the XOR output is equivalent to a PWM. (click to zoom)
• [
• ](https://electrical.codidact.com/uploads/6bdrMJQBbLLbZvD8EJo2Fq1L)
• Given a master clock $f_{ m CPU}$, the available triangle frequencies are $2 f_{ m CPU} / (n^2 - 1)$, where $n$ is an odd integer. The two clocks are set to $f_{ m CPU}/(n+1)$ and $f_{ m CPU}/(n-1)$, to make the dividers even numbers (to allow 50% duty cycles on A and B).
• The low-pass filter design is also parametrized by $n$. If we define passband at the triangle’s 5th harmonic, then non dimensional value $f_{\rm STOP} / f_{\rm PASS}$, representing the transition band, comes out to $n/5$.
• The non dimensional transition band corresponds to "filter complexity". A narrower transition band places more demands on the filter design. Given a lower limit of this value, the practical upper limit for the triangle frequency can then be derived as
• $$ \frac{f_{\rm TRIANGLE(max)}}{f_{\rm CPU}} = \frac{2}{25} \left(\frac{f_{\rm PASS}}{f_{\rm STOP}}\right)^2$$
• The table below uses this formula to show typical limits of the application:
• | min acceptable $f_{\rm STOP}/f_{\rm PASS}$ | max $f_{\rm TRIANGLE}/f_{\rm CPU}$ |
• |- | - |
• | 20 | 1 / 5000 |
• | 40 | 1 / 20000 |
• | 60 (shown in example) | 1 / 45000 |
• | 80 | 1 / 80000 |
• | 100 | 1 / 125000 |
• -----
• Example Circuit producing 199Hz from 10MHz f_cpu
• 
• Simulation of above circuit. 0-1V inputs produce 12mV - 988 mV peaks
• 
• Detail showing less than 1% ripple.
• 
• -----
• Additional details of the analysis, and example showing the design calculation, are [here (pdf file, 5 pages)](https://gofile.io/d/hMXWWc).

#9: Post edited by Pete W‭ · 2020-12-30T17:52:24Z (over 3 years ago)

Raw

Markdown

• What follows is a proposed concept of a simple (in principle!) way to generate a fixed-amplitude triangle wave, using two clocks, an XOR gate, and not using any processor cycles.
• It is practical in the low-mid-100-Hz ballpark, with typical mcu clocks. Motivating application is dither waveform for solenoid valve control signals.
• ----
• SUMMARY
• Two timers output two clocks A, B, with fixed 50% duty cycle. XOR(A,B) produces a symmetrical PWM triangle wave, with modulation frequency at ($f_{\rm A} + f_{\rm B})$ , and triangle frequency at $(f_{\rm A} - f_{\rm B})$. No other additional hardware. Illustrated below, showing how the XOR output is equivalent to a PWM. (click to zoom)
• [
• ](https://electrical.codidact.com/uploads/6bdrMJQBbLLbZvD8EJo2Fq1L)
• Given a master clock $f_{ m CPU}$, the available triangle frequencies are $2 f_{ m CPU} / (n^2 - 1)$, where $n$ is an odd integer. The two clocks are set to $f_{ m CPU}/(n+1)$ and $f_{ m CPU}/(n-1)$.
• The low-pass filter design is also parametrized by $n$. If we define passband at the triangle’s 5th harmonic, then non dimensional value $f_{\rm STOP} / f_{\rm PASS}$, representing the transition band, comes out to $n/5$.
• The non dimensional transition band corresponds to "filter complexity". A narrower transition band places more demands on the filter design. Given a lower limit of this value, the practical upper limit for the triangle frequency can then be derived as
• $$ \frac{f_{\rm TRIANGLE(max)}}{f_{\rm CPU}} = \frac{2}{25} \left(\frac{f_{\rm PASS}}{f_{\rm STOP}}\right)^2$$
• The table below uses this formula to show typical limits of the application:
• | min acceptable $f_{\rm STOP}/f_{\rm PASS}$ | max $f_{\rm TRIANGLE}/f_{\rm CPU}$ |
• |- | - |
• | 20 | 1 / 5000 |
• | 40 | 1 / 20000 |
• | 60 (shown in example) | 1 / 45000 |
• | 80 | 1 / 80000 |
• | 100 | 1 / 125000 |
• -----
• Example Circuit producing 199Hz from 10MHz f_cpu
• 
• Simulation of above circuit. 0-1V inputs produce 12mV - 988 mV peaks
• 
• Detail showing less than 1% ripple.
• 
• -----
• Additional details of the analysis, and example showing the design calculation, are [here (pdf file, 5 pages)](https://gofile.io/d/hMXWWc).

• What follows is a proposed concept of a simple (in principle!) way to generate a fixed-amplitude triangle wave, using two clocks, an XOR gate, and not using any processor cycles.
• It is practical in the low-mid-100-Hz ballpark, with typical mcu clocks. Motivating application is dither waveform for solenoid valve control signals.
• ----
• SUMMARY
• Two timers output two clocks A, B, with fixed 50% duty cycle. XOR(A,B) produces a symmetrical PWM triangle wave, with modulation frequency at ($f_{\rm A} + f_{\rm B})$ , and triangle frequency at $(f_{\rm A} - f_{\rm B})$. No other additional hardware. Illustrated below, showing how the XOR output is equivalent to a PWM. (click to zoom)
• [
• ](https://electrical.codidact.com/uploads/6bdrMJQBbLLbZvD8EJo2Fq1L)
• Given a master clock $f_{ m CPU}$, the available triangle frequencies are $2 f_{ m CPU} / (n^2 - 1)$, where $n$ is an odd integer. The two clocks are set to $f_{ m CPU}/(n+1)$ and $f_{ m CPU}/(n-1)$, to make the dividers even numbers (to allow 50% duty cycle).
• The low-pass filter design is also parametrized by $n$. If we define passband at the triangle’s 5th harmonic, then non dimensional value $f_{\rm STOP} / f_{\rm PASS}$, representing the transition band, comes out to $n/5$.
• The non dimensional transition band corresponds to "filter complexity". A narrower transition band places more demands on the filter design. Given a lower limit of this value, the practical upper limit for the triangle frequency can then be derived as
• $$ \frac{f_{\rm TRIANGLE(max)}}{f_{\rm CPU}} = \frac{2}{25} \left(\frac{f_{\rm PASS}}{f_{\rm STOP}}\right)^2$$
• The table below uses this formula to show typical limits of the application:
• | min acceptable $f_{\rm STOP}/f_{\rm PASS}$ | max $f_{\rm TRIANGLE}/f_{\rm CPU}$ |
• |- | - |
• | 20 | 1 / 5000 |
• | 40 | 1 / 20000 |
• | 60 (shown in example) | 1 / 45000 |
• | 80 | 1 / 80000 |
• | 100 | 1 / 125000 |
• -----
• Example Circuit producing 199Hz from 10MHz f_cpu
• 
• Simulation of above circuit. 0-1V inputs produce 12mV - 988 mV peaks
• 
• Detail showing less than 1% ripple.
• 
• -----
• Additional details of the analysis, and example showing the design calculation, are [here (pdf file, 5 pages)](https://gofile.io/d/hMXWWc).

#8: Post edited by Pete W‭ · 2020-12-30T17:46:50Z (over 3 years ago)

Raw

Markdown

• What follows is a proposed concept of a simple (in principle!) way to generate a fixed-amplitude triangle wave, using two clocks, an XOR gate, and not using any processor cycles.
• It is practical in the low-mid-100-Hz ballpark, with typical mcu clocks. Motivating application is dither waveform for solenoid valve control signals.
• ----
• SUMMARY
• Two timers output two clocks A, B, with fixed 50% duty cycle. XOR(A,B) produces a symmetrical PWM triangle wave, with modulation frequency at ($f_{\rm A} + f_{\rm B})$ , and triangle frequency at $(f_{\rm A} - f_{\rm B})$. No other additional hardware. Illustrated below, showing how the XOR output is equivalent to a PWM. (click to zoom)
• [
• ](https://electrical.codidact.com/uploads/6bdrMJQBbLLbZvD8EJo2Fq1L)
• Given a master clock $f_{\rm CPU}$, the available triangle frequencies are $2 f_{\rm CPU} / (n^2 - 1)$, where $n$ is an odd integer. The two clocks are set to $f_{\rm CPU}/(n+1)$ and $f_{\rm CPU}/(n-1)$.
• The low-pass filter design is also parametrized by $n$. If we define passband at the triangle’s 5th harmonic, then non dimensional value $f_{\rm STOP} / f_{\rm PASS}$, representing the transition band, comes out to $n/5$.
• The non dimensional transition band corresponds to "filter complexity". A narrower transition band places more demands on the filter design. Given a lower limit of this value, the practical upper limit for the triangle frequency can then be derived as
• $$ \frac{f_{\rm TRIANGLE(max)}}{f_{\rm CPU}} = \frac{2}{25} \left(\frac{f_{\rm PASS}}{f_{\rm STOP}}\right)^2$$
• The table below uses this formula to show typical limits of the application:
• | min acceptable $f_{\rm STOP}/f_{\rm PASS}$ | max $f_{\rm TRIANGLE}/f_{\rm CPU}$ |
• |- | - |
• | 20 | 1 / 5000 |
• | 40 | 1 / 20000 |
• | 60 (recommended) | 1 / 45000 |
• | 80 | 1 / 80000 |
• | 100 | 1 / 125000 |
• -----
• Example Circuit producing 199Hz from 10MHz f_cpu
• 
• Simulation of above circuit. 0-1V inputs produce 12mV - 988 mV peaks
• 
• Detail showing less than 1% ripple.
• 
• -----
• Additional details of the analysis, and example showing the design calculation, are [here (pdf file, 5 pages)](https://gofile.io/d/hMXWWc).

• What follows is a proposed concept of a simple (in principle!) way to generate a fixed-amplitude triangle wave, using two clocks, an XOR gate, and not using any processor cycles.
• It is practical in the low-mid-100-Hz ballpark, with typical mcu clocks. Motivating application is dither waveform for solenoid valve control signals.
• ----
• SUMMARY
• Two timers output two clocks A, B, with fixed 50% duty cycle. XOR(A,B) produces a symmetrical PWM triangle wave, with modulation frequency at ($f_{\rm A} + f_{\rm B})$ , and triangle frequency at $(f_{\rm A} - f_{\rm B})$. No other additional hardware. Illustrated below, showing how the XOR output is equivalent to a PWM. (click to zoom)
• [
• ](https://electrical.codidact.com/uploads/6bdrMJQBbLLbZvD8EJo2Fq1L)
• Given a master clock $f_{\rm CPU}$, the available triangle frequencies are $2 f_{\rm CPU} / (n^2 - 1)$, where $n$ is an odd integer. The two clocks are set to $f_{\rm CPU}/(n+1)$ and $f_{\rm CPU}/(n-1)$.
• The low-pass filter design is also parametrized by $n$. If we define passband at the triangle’s 5th harmonic, then non dimensional value $f_{\rm STOP} / f_{\rm PASS}$, representing the transition band, comes out to $n/5$.
• The non dimensional transition band corresponds to "filter complexity". A narrower transition band places more demands on the filter design. Given a lower limit of this value, the practical upper limit for the triangle frequency can then be derived as
• $$ \frac{f_{\rm TRIANGLE(max)}}{f_{\rm CPU}} = \frac{2}{25} \left(\frac{f_{\rm PASS}}{f_{\rm STOP}}\right)^2$$
• The table below uses this formula to show typical limits of the application:
• | min acceptable $f_{\rm STOP}/f_{\rm PASS}$ | max $f_{\rm TRIANGLE}/f_{\rm CPU}$ |
• |- | - |
• | 20 | 1 / 5000 |
• | 40 | 1 / 20000 |
• | 60 (shown in example) | 1 / 45000 |
• | 80 | 1 / 80000 |
• | 100 | 1 / 125000 |
• -----
• Example Circuit producing 199Hz from 10MHz f_cpu
• 
• Simulation of above circuit. 0-1V inputs produce 12mV - 988 mV peaks
• 
• Detail showing less than 1% ripple.
• 
• -----
• Additional details of the analysis, and example showing the design calculation, are [here (pdf file, 5 pages)](https://gofile.io/d/hMXWWc).

#7: Post edited by Pete W‭ · 2020-12-30T17:45:36Z (over 3 years ago)

Raw

Markdown

• What follows is a proposed concept of a simple (in principle!) way to generate a fixed-amplitude triangle wave, using two clocks, an XOR gate, and not using any processor cycles.
• It is practical in the low-mid-100-Hz ballpark, with typical mcu clocks. Motivating application is dither waveform for solenoid valve control signals.
• ----
• SUMMARY
• Two timers output two clocks A, B, with fixed 50% duty cycle. XOR(A,B) produces a symmetrical PWM triangle wave, with modulation frequency at ($f_{ m A} + f_{ m B})$ , and triangle frequency at $(f_{ m A} - f_{ m B})$. No other additional hardware. Illustrated below, showing how the XOR output is a PWM. (click to zoom)
• [
• ](https://electrical.codidact.com/uploads/6bdrMJQBbLLbZvD8EJo2Fq1L)
• Given a master clock $f_{\rm CPU}$, the available triangle frequencies are $2 f_{\rm CPU} / (n^2 - 1)$, where $n$ is an odd integer. The two clocks are set to $f_{\rm CPU}/(n+1)$ and $f_{\rm CPU}/(n-1)$.
• The low-pass filter design is also parametrized by $n$. If we define passband at the triangle’s 5th harmonic, then non dimensional value $f_{\rm STOP} / f_{\rm PASS}$, representing the transition band, comes out to $n/5$.
• The non dimensional transition band corresponds to "filter complexity". A narrower transition band places more demands on the filter design. Given a lower limit of this value, the practical upper limit for the triangle frequency can then be derived as
• $$ \frac{f_{\rm TRIANGLE(max)}}{f_{\rm CPU}} = \frac{2}{25} \left(\frac{f_{\rm PASS}}{f_{\rm STOP}}\right)^2$$
• The table below uses this formula to show typical limits of the application:
• | min acceptable $f_{\rm STOP}/f_{\rm PASS}$ | max $f_{\rm TRIANGLE}/f_{\rm CPU}$ |
• |- | - |
• | 20 | 1 / 5000 |
• | 40 | 1 / 20000 |
• | 60 (recommended) | 1 / 45000 |
• | 80 | 1 / 80000 |
• | 100 | 1 / 125000 |
• -----
• Example Circuit producing 199Hz from 10MHz f_cpu
• 
• Simulation of above circuit. 0-1V inputs produce 12mV - 988 mV peaks
• 
• Detail showing less than 1% ripple.
• 
• -----
• Additional details of the analysis, and example showing the design calculation, are [here (pdf file, 5 pages)](https://gofile.io/d/hMXWWc).

• What follows is a proposed concept of a simple (in principle!) way to generate a fixed-amplitude triangle wave, using two clocks, an XOR gate, and not using any processor cycles.
• It is practical in the low-mid-100-Hz ballpark, with typical mcu clocks. Motivating application is dither waveform for solenoid valve control signals.
• ----
• SUMMARY
• Two timers output two clocks A, B, with fixed 50% duty cycle. XOR(A,B) produces a symmetrical PWM triangle wave, with modulation frequency at ($f_{ m A} + f_{ m B})$ , and triangle frequency at $(f_{ m A} - f_{ m B})$. No other additional hardware. Illustrated below, showing how the XOR output is equivalent to a PWM. (click to zoom)
• [
• ](https://electrical.codidact.com/uploads/6bdrMJQBbLLbZvD8EJo2Fq1L)
• Given a master clock $f_{\rm CPU}$, the available triangle frequencies are $2 f_{\rm CPU} / (n^2 - 1)$, where $n$ is an odd integer. The two clocks are set to $f_{\rm CPU}/(n+1)$ and $f_{\rm CPU}/(n-1)$.
• The low-pass filter design is also parametrized by $n$. If we define passband at the triangle’s 5th harmonic, then non dimensional value $f_{\rm STOP} / f_{\rm PASS}$, representing the transition band, comes out to $n/5$.
• The non dimensional transition band corresponds to "filter complexity". A narrower transition band places more demands on the filter design. Given a lower limit of this value, the practical upper limit for the triangle frequency can then be derived as
• $$ \frac{f_{\rm TRIANGLE(max)}}{f_{\rm CPU}} = \frac{2}{25} \left(\frac{f_{\rm PASS}}{f_{\rm STOP}}\right)^2$$
• The table below uses this formula to show typical limits of the application:
• | min acceptable $f_{\rm STOP}/f_{\rm PASS}$ | max $f_{\rm TRIANGLE}/f_{\rm CPU}$ |
• |- | - |
• | 20 | 1 / 5000 |
• | 40 | 1 / 20000 |
• | 60 (recommended) | 1 / 45000 |
• | 80 | 1 / 80000 |
• | 100 | 1 / 125000 |
• -----
• Example Circuit producing 199Hz from 10MHz f_cpu
• 
• Simulation of above circuit. 0-1V inputs produce 12mV - 988 mV peaks
• 
• Detail showing less than 1% ripple.
• 
• -----
• Additional details of the analysis, and example showing the design calculation, are [here (pdf file, 5 pages)](https://gofile.io/d/hMXWWc).

#6: Post edited by Pete W‭ · 2020-12-30T17:45:04Z (over 3 years ago)

Raw

Markdown

• What follows is a proposed concept of a simple (in principle!) way to generate a fixed-amplitude triangle wave, using two clocks, an XOR gate, and not using any processor cycles.
• It is practical in the low-mid-100-Hz ballpark, with typical mcu clocks. Motivating application is dither waveform for solenoid valve control signals.
• ----
• SUMMARY
• Two timers output two clocks A, B, with fixed 50% duty cycle. XOR(A,B) produces a symmetrical PWM triangle wave, with modulation frequency at ($f_{\rm A} + f_{\rm B})$ , and triangle frequency at $(f_{\rm A} - f_{\rm B})$. No other additional hardware. Illustrated below, showing how the XOR output is a PWM. (click to zoom)
• [
• ](https://electrical.codidact.com/uploads/6bdrMJQBbLLbZvD8EJo2Fq1L)
• Given a master clock $f_{\rm CPU}$, the available triangle frequencies are $2 f_{\rm CPU} / (n^2 - 1)$, where $n$ is an odd integer. The two clocks are set to $f_{\rm CPU}/(n+1)$ and $f_{\rm CPU}/(n-1)$.
• The low-pass filter design is also parametrized by $n$. If we define passband at the triangle’s 5th harmonic, then non dimensional value $f_{\rm STOP} / f_{\rm PASS}$, representing the transition band, comes out to $n/5$.
• The non dimensional transition band corresponds to "filter complexity". A narrower transition band places more demands on the filter design. Given a lower limit of this value, the practical upper limit for the triangle frequency can then be derived as $$ \frac{f_{\rm TRIANGLE(max)}}{f_{\rm CPU}} = \frac{2}{25} (\frac{f_{\rm PASS}}{f_{\rm STOP}})^2$$
• ----
• Typical values of $f_{\rm TRIANGLE(max)}$
• | min acceptable $f_{ m STOP}/f_{ m PASS}$ | max $f_{ m TRIANGLE(max)}/f_{ m CPU}$ |
• |- | - |
• | 20 | 1 / 5000 |
• | 40 | 1 / 20000 |
• | 60 (recommended) | 1 / 45000 |
• | 80 | 1 / 80000 |
• | 100 | 1 / 125000 |
• -----
• Example Circuit producing 199Hz from 10MHz f_cpu
• 
• Simulation of above circuit. 0-1V inputs produce 12mV - 988 mV peaks
• 
• Detail showing less than 1% ripple.
• 
• -----
• Additional details of the analysis, and example showing the design calculation, are [here (pdf file, 5 pages)](https://gofile.io/d/hMXWWc).

• What follows is a proposed concept of a simple (in principle!) way to generate a fixed-amplitude triangle wave, using two clocks, an XOR gate, and not using any processor cycles.
• It is practical in the low-mid-100-Hz ballpark, with typical mcu clocks. Motivating application is dither waveform for solenoid valve control signals.
• ----
• SUMMARY
• Two timers output two clocks A, B, with fixed 50% duty cycle. XOR(A,B) produces a symmetrical PWM triangle wave, with modulation frequency at ($f_{\rm A} + f_{\rm B})$ , and triangle frequency at $(f_{\rm A} - f_{\rm B})$. No other additional hardware. Illustrated below, showing how the XOR output is a PWM. (click to zoom)
• [
• ](https://electrical.codidact.com/uploads/6bdrMJQBbLLbZvD8EJo2Fq1L)
• Given a master clock $f_{\rm CPU}$, the available triangle frequencies are $2 f_{\rm CPU} / (n^2 - 1)$, where $n$ is an odd integer. The two clocks are set to $f_{\rm CPU}/(n+1)$ and $f_{\rm CPU}/(n-1)$.
• The low-pass filter design is also parametrized by $n$. If we define passband at the triangle’s 5th harmonic, then non dimensional value $f_{\rm STOP} / f_{\rm PASS}$, representing the transition band, comes out to $n/5$.
• The non dimensional transition band corresponds to "filter complexity". A narrower transition band places more demands on the filter design. Given a lower limit of this value, the practical upper limit for the triangle frequency can then be derived as
• $$ \frac{f_{\rm TRIANGLE(max)}}{f_{\rm CPU}} = \frac{2}{25} \left(\frac{f_{\rm PASS}}{f_{\rm STOP}}\right)^2$$
• The table below uses this formula to show typical limits of the application:
• | min acceptable $f_{ m STOP}/f_{ m PASS}$ | max $f_{ m TRIANGLE}/f_{ m CPU}$ |
• |- | - |
• | 20 | 1 / 5000 |
• | 40 | 1 / 20000 |
• | 60 (recommended) | 1 / 45000 |
• | 80 | 1 / 80000 |
• | 100 | 1 / 125000 |
• -----
• Example Circuit producing 199Hz from 10MHz f_cpu
• 
• Simulation of above circuit. 0-1V inputs produce 12mV - 988 mV peaks
• 
• Detail showing less than 1% ripple.
• 
• -----
• Additional details of the analysis, and example showing the design calculation, are [here (pdf file, 5 pages)](https://gofile.io/d/hMXWWc).

#5: Post edited by Pete W‭ · 2020-12-30T17:39:43Z (over 3 years ago)

Raw

Markdown

• What follows is a proposed concept of a simple (in principle!) way to generate a fixed-amplitude triangle wave, using two clocks, an XOR gate, and not using any processor cycles.
• It is practical in the low-mid-100-Hz ballpark, with typical mcu clocks. Motivating application is dither waveform for solenoid valve control signals.
• ----
• SUMMARY
• Two timers output two clocks A, B, with fixed 50% duty cycle. XOR(A,B) produces a symmetrical PWM triangle wave, with modulation frequency at ($f_{\rm A} + f_{\rm B})$ , and triangle frequency at $(f_{\rm A} - f_{\rm B})$. No other additional hardware. Illustrated below, showing how the XOR output is a PWM. (click to zoom)
• [
• ](https://electrical.codidact.com/uploads/6bdrMJQBbLLbZvD8EJo2Fq1L)
• Given a master clock f_cpu, the available triangle frequencies are
• $2 f_{ m cpu} / (n^2 - 1)$, where $n$ is an odd integer. The two clocks are set to $f_{ m cpu}/(n+1)$ and $f_{ m cpu}/(n-1)$.
• The low-pass filter design is also parametrized by $n$. If we define passband at the triangle’s 5th harmonic, then non dimensional value $f_{ m stop} / f_{ m pass}$, representing the transition band, comes out to $n/5$.
• The non dimensional transition band corresponds to "filter complexity". A narrower transition band places more demands on the filter design. Given a lower limit of this value, the practical upper limit for the triangle frequency can then be derived relative to f_cpu, as $$\frac{2 f_{ m pass}^2}{25 f_{ m stop}^2}.$$
• Typical values shown below.
• ----
• Practical limit of f_triangle
• | min acceptable $f_{ m stop}/f_{ m pass}$ | max $f_{ m triangle}/f_{ m cpu}$ |
• |- | - |
• | 20 | 1 / 5000 |
• | 40 | 1 / 20000 |
• | 60 (recommended) | 1 / 45000 |
• | 80 | 1 / 80000 |
• | 100 | 1 / 125000 |
• -----
• Example Circuit producing 199Hz from 10MHz f_cpu
• 
• Simulation of above circuit. 0-1V inputs produce 12mV - 988 mV peaks
• 
• Detail showing less than 1% ripple.
• 
• -----
• Additional details of the analysis, and example showing the design calculation, are [here (pdf file, 5 pages)](https://gofile.io/d/hMXWWc).

• What follows is a proposed concept of a simple (in principle!) way to generate a fixed-amplitude triangle wave, using two clocks, an XOR gate, and not using any processor cycles.
• It is practical in the low-mid-100-Hz ballpark, with typical mcu clocks. Motivating application is dither waveform for solenoid valve control signals.
• ----
• SUMMARY
• Two timers output two clocks A, B, with fixed 50% duty cycle. XOR(A,B) produces a symmetrical PWM triangle wave, with modulation frequency at ($f_{\rm A} + f_{\rm B})$ , and triangle frequency at $(f_{\rm A} - f_{\rm B})$. No other additional hardware. Illustrated below, showing how the XOR output is a PWM. (click to zoom)
• [
• ](https://electrical.codidact.com/uploads/6bdrMJQBbLLbZvD8EJo2Fq1L)
• Given a master clock $f_{\rm CPU}$, the available triangle frequencies are $2 f_{ m CPU} / (n^2 - 1)$, where $n$ is an odd integer. The two clocks are set to $f_{ m CPU}/(n+1)$ and $f_{ m CPU}/(n-1)$.
• The low-pass filter design is also parametrized by $n$. If we define passband at the triangle’s 5th harmonic, then non dimensional value $f_{ m STOP} / f_{ m PASS}$, representing the transition band, comes out to $n/5$.
• The non dimensional transition band corresponds to "filter complexity". A narrower transition band places more demands on the filter design. Given a lower limit of this value, the practical upper limit for the triangle frequency can then be derived as $$ \frac{f_{ m TRIANGLE(max)}}{f_{\rm CPU}} = \frac{2}{25} (\frac{f_{\rm PASS}}{f_{ m STOP}})^2$$
• ----
• Typical values of $f_{\rm TRIANGLE(max)}$
• | min acceptable $f_{ m STOP}/f_{ m PASS}$ | max $f_{ m TRIANGLE(max)}/f_{ m CPU}$ |
• |- | - |
• | 20 | 1 / 5000 |
• | 40 | 1 / 20000 |
• | 60 (recommended) | 1 / 45000 |
• | 80 | 1 / 80000 |
• | 100 | 1 / 125000 |
• -----
• Example Circuit producing 199Hz from 10MHz f_cpu
• 
• Simulation of above circuit. 0-1V inputs produce 12mV - 988 mV peaks
• 
• Detail showing less than 1% ripple.
• 
• -----
• Additional details of the analysis, and example showing the design calculation, are [here (pdf file, 5 pages)](https://gofile.io/d/hMXWWc).

#4: Post edited by Pete W‭ · 2020-12-30T17:28:30Z (over 3 years ago)

Raw

Markdown

• What follows is a proposed concept of a simple (in principle!) way to generate a fixed-amplitude triangle wave, using two clocks, an XOR gate, and not using any processor cycles.
• It is practical in the low-mid-100-Hz ballpark, with typical mcu clocks. Motivating application is dither waveform for solenoid valve control signals.
• ----
• SUMMARY
• Two timers output two clocks A, B, with fixed 50% duty cycle. XOR(A,B) produces a symmetrical PWM triangle wave, with modulation frequency at ($f_{\rm A} + f_{\rm B})$ , and triangle frequency at $(f_{\rm A} - f_{\rm B})$. No other additional hardware. Illustrated below, showing how the XOR output is a PWM. (click to zoom)
• [
• ](https://electrical.codidact.com/uploads/6bdrMJQBbLLbZvD8EJo2Fq1L)
• Given a master clock f_cpu, the available triangle frequencies are
• $2 f_{ m cpu} / (n^2 - 1)$, where “n” is an odd integer. The two clocks are set to $f_{ m cpu}/(n+1)$ and $f_{ m cpu}/(n-1)$.
• The low-pass filter design is also parametrized by “n”. If we define passband at the triangle’s 5th harmonic, then non dimensional value (f_stop / f_pass), representing the transition band, comes out to n/5.
• The non dimensional transition band corresponds to "filter complexity". A narrower transition band places more demands on the filter design. Given a lower limit of this value, the practical upper limit for the triangle frequency can then be derived relative to f_cpu, as $$\frac{2 f_{\rm pass}^2}{25 f_{\rm stop}^2}.$$
• Typical values shown below.
• ----
• Practical limit of f_triangle
• | min acceptable (f_stop / f_pass) | max (f_triangle / f_cpu) |
• |- | - |
• | 20 | 1 / 5000 |
• | 40 | 1 / 20000 |
• | 60 (recommended) | 1 / 45000 |
• | 80 | 1 / 80000 |
• | 100 | 1 / 125000 |
• -----
• Example Circuit producing 199Hz from 10MHz f_cpu
• 
• Simulation of above circuit. 0-1V inputs produce 12mV - 988 mV peaks
• 
• Detail showing less than 1% ripple.
• 
• -----
• Additional details of the analysis, and example showing the design calculation, are [here (pdf file, 5 pages)](https://gofile.io/d/hMXWWc). The site format is a little limiting unfortunately.

• What follows is a proposed concept of a simple (in principle!) way to generate a fixed-amplitude triangle wave, using two clocks, an XOR gate, and not using any processor cycles.
• It is practical in the low-mid-100-Hz ballpark, with typical mcu clocks. Motivating application is dither waveform for solenoid valve control signals.
• ----
• SUMMARY
• Two timers output two clocks A, B, with fixed 50% duty cycle. XOR(A,B) produces a symmetrical PWM triangle wave, with modulation frequency at ($f_{\rm A} + f_{\rm B})$ , and triangle frequency at $(f_{\rm A} - f_{\rm B})$. No other additional hardware. Illustrated below, showing how the XOR output is a PWM. (click to zoom)
• [
• ](https://electrical.codidact.com/uploads/6bdrMJQBbLLbZvD8EJo2Fq1L)
• Given a master clock f_cpu, the available triangle frequencies are
• $2 f_{ m cpu} / (n^2 - 1)$, where $n$ is an odd integer. The two clocks are set to $f_{ m cpu}/(n+1)$ and $f_{ m cpu}/(n-1)$.
• The low-pass filter design is also parametrized by $n$. If we define passband at the triangle’s 5th harmonic, then non dimensional value $f_{\rm stop} / f_{\rm pass}$, representing the transition band, comes out to $n/5$.
• The non dimensional transition band corresponds to "filter complexity". A narrower transition band places more demands on the filter design. Given a lower limit of this value, the practical upper limit for the triangle frequency can then be derived relative to f_cpu, as $$\frac{2 f_{\rm pass}^2}{25 f_{\rm stop}^2}.$$
• Typical values shown below.
• ----
• Practical limit of f_triangle
• | min acceptable $f_{\rm stop}/f_{\rm pass}$ | max $f_{\rm triangle}/f_{\rm cpu}$ |
• |- | - |
• | 20 | 1 / 5000 |
• | 40 | 1 / 20000 |
• | 60 (recommended) | 1 / 45000 |
• | 80 | 1 / 80000 |
• | 100 | 1 / 125000 |
• -----
• Example Circuit producing 199Hz from 10MHz f_cpu
• 
• Simulation of above circuit. 0-1V inputs produce 12mV - 988 mV peaks
• 
• Detail showing less than 1% ripple.
• 
• -----
• Additional details of the analysis, and example showing the design calculation, are [here (pdf file, 5 pages)](https://gofile.io/d/hMXWWc).

#3: Post edited by Pete W‭ · 2020-12-30T17:24:43Z (over 3 years ago)

Raw

Markdown

• What follows is a proposed concept of a simple (in principle!) way to generate a fixed-amplitude triangle wave, using two clocks, an XOR gate, and not using any processor cycles.
• It is practical in the low-mid-100-Hz ballpark, with typical mcu clocks. Motivating application is dither waveform for solenoid valve control signals.
• ----
• SUMMARY
• Two timers output two clocks A, B, with fixed 50% duty cycle. XOR(A,B) produces a symmetrical PWM triangle wave, with modulation frequency at the sum of the f_A and f_B, and triangle frequency at the difference. No other additional hardware. Illustrated below -- the resulting waveform on the bottom is a PWM. (click to zoom)
• [
• ](https://electrical.codidact.com/uploads/6bdrMJQBbLLbZvD8EJo2Fq1L)
• Given a master clock f_cpu, the available triangle frequencies are
• $2 f_{\rm cpu} / (n^2 - 1)$, where “n” is an odd integer. The two clocks are set to $f_{\rm cpu}/(n+1)$ and $f_{\rm cpu}/(n-1)$.
• The low-pass filter design is also parametrized by “n”. If we define passband at the triangle’s 5th harmonic, then non dimensional value (f_stop / f_pass), representing the transition band, comes out to n/5.
• The non dimensional transition band corresponds to "filter complexity". A narrower transition band places more demands on the filter design. Given a lower limit of this value, the practical upper limit for the triangle frequency can then be derived relative to f_cpu, as $$\frac{2 f_{\rm pass}^2}{25 f_{\rm stop}^2}.$$
• Typical values shown below.
• ----
• Practical limit of f_triangle
• | min acceptable (f_stop / f_pass) | max (f_triangle / f_cpu) |
• |- | - |
• | 20 | 1 / 5000 |
• | 40 | 1 / 20000 |
• | 60 (recommended) | 1 / 45000 |
• | 80 | 1 / 80000 |
• | 100 | 1 / 125000 |
• -----
• Example Circuit producing 199Hz from 10MHz f_cpu
• 
• Simulation of above circuit. 0-1V inputs produce 12mV - 988 mV peaks
• 
• Detail showing less than 1% ripple.
• 
• -----
• Additional details of the analysis, and example showing the design calculation, are [here (pdf file, 5 pages)](https://gofile.io/d/hMXWWc). The site format is a little limiting unfortunately.

• What follows is a proposed concept of a simple (in principle!) way to generate a fixed-amplitude triangle wave, using two clocks, an XOR gate, and not using any processor cycles.
• It is practical in the low-mid-100-Hz ballpark, with typical mcu clocks. Motivating application is dither waveform for solenoid valve control signals.
• ----
• SUMMARY
• Two timers output two clocks A, B, with fixed 50% duty cycle. XOR(A,B) produces a symmetrical PWM triangle wave, with modulation frequency at ($f_{\rm A} + f_{\rm B})$ , and triangle frequency at $(f_{\rm A} - f_{\rm B})$. No other additional hardware. Illustrated below, showing how the XOR output is a PWM. (click to zoom)
• [
• ](https://electrical.codidact.com/uploads/6bdrMJQBbLLbZvD8EJo2Fq1L)
• Given a master clock f_cpu, the available triangle frequencies are
• $2 f_{\rm cpu} / (n^2 - 1)$, where “n” is an odd integer. The two clocks are set to $f_{\rm cpu}/(n+1)$ and $f_{\rm cpu}/(n-1)$.
• The low-pass filter design is also parametrized by “n”. If we define passband at the triangle’s 5th harmonic, then non dimensional value (f_stop / f_pass), representing the transition band, comes out to n/5.
• The non dimensional transition band corresponds to "filter complexity". A narrower transition band places more demands on the filter design. Given a lower limit of this value, the practical upper limit for the triangle frequency can then be derived relative to f_cpu, as $$\frac{2 f_{\rm pass}^2}{25 f_{\rm stop}^2}.$$
• Typical values shown below.
• ----
• Practical limit of f_triangle
• | min acceptable (f_stop / f_pass) | max (f_triangle / f_cpu) |
• |- | - |
• | 20 | 1 / 5000 |
• | 40 | 1 / 20000 |
• | 60 (recommended) | 1 / 45000 |
• | 80 | 1 / 80000 |
• | 100 | 1 / 125000 |
• -----
• Example Circuit producing 199Hz from 10MHz f_cpu
• 
• Simulation of above circuit. 0-1V inputs produce 12mV - 988 mV peaks
• 
• Detail showing less than 1% ripple.
• 
• -----
• Additional details of the analysis, and example showing the design calculation, are [here (pdf file, 5 pages)](https://gofile.io/d/hMXWWc). The site format is a little limiting unfortunately.

#2: Post edited by coquelicot‭ · 2020-12-30T17:20:42Z (over 3 years ago)
Formulas in Latex + a slight simplification of the (2/25)/ (f_stop/f_start)^2 formula

Raw

Markdown

PWM Triangle Wave from two clocks

• What follows is a proposed concept of a simple (in principle!) way to generate a fixed-amplitude triangle wave, using two clocks, an XOR gate, and not using any processor cycles.
• It is practical in the low-mid-100-Hz ballpark, with typical mcu clocks. Motivating application is dither waveform for solenoid valve control signals.
• ----
• SUMMARY
• Two timers output two clocks A, B, with fixed 50% duty cycle. XOR(A,B) produces a symmetrical PWM triangle wave, with modulation frequency at (f_A + f_B), and triangle frequency at (f_A - f_B). No other additional hardware. Illustrated below -- the resulting waveform on the bottom is a PWM. (click to zoom)
• [
• ](https://electrical.codidact.com/uploads/6bdrMJQBbLLbZvD8EJo2Fq1L)
• Given a master clock f_cpu, the available triangle frequencies are 2 * f_cpu / (n^2 - 1), where “n” is an odd integer. The two clocks are set to f_cpu/(n+1) and f_cpu/(n-1).
• The low-pass filter design is also parametrized by “n”. If we define passband at the triangle’s 5th harmonic, then nondimensional value (f_stop / f_pass), representing the transition band, comes out to n/5.
• The nondimensional transition band corresponds to "filter complexity". A narrower transition band places more demands on the filter design. Given a lower limit of this value, the practical upper limit for the triangle frequency can then be derived relative to f_cpu, as (2/25)/(f_stop/f_pass)^2 . Typical values shown below.
• ----
• Practical limit of f_triangle
• | min acceptable (f_stop / f_pass) | max (f_triangle / f_cpu) |
• |- | - |
• | 20 | 1 / 5000 |
• | 40 | 1 / 20000 |
• | 60 (recommended) | 1 / 45000 |
• | 80 | 1 / 80000 |
• | 100 | 1 / 125000 |
• -----
• Example Circuit producing 199Hz from 10MHz f_cpu
• 
• Simulation of above circuit. 0-1V inputs produce 12mV - 988 mV peaks
• 
• Detail showing less than 1% ripple.
• 
• -----
• Additional details of the analysis, and example showing the design calculation, are [here (pdf file, 5 pages)](https://gofile.io/d/hMXWWc). I don't know this site's markup features well enough yet to get it the local format easily...

• What follows is a proposed concept of a simple (in principle!) way to generate a fixed-amplitude triangle wave, using two clocks, an XOR gate, and not using any processor cycles.
• It is practical in the low-mid-100-Hz ballpark, with typical mcu clocks. Motivating application is dither waveform for solenoid valve control signals.
• ----
• SUMMARY
• Two timers output two clocks A, B, with fixed 50% duty cycle. XOR(A,B) produces a symmetrical PWM triangle wave, with modulation frequency at the sum of the f_A and f_B, and triangle frequency at the difference. No other additional hardware. Illustrated below -- the resulting waveform on the bottom is a PWM. (click to zoom)
• [
• ](https://electrical.codidact.com/uploads/6bdrMJQBbLLbZvD8EJo2Fq1L)
• Given a master clock f_cpu, the available triangle frequencies are
• $2 f_{\rm cpu} / (n^2 - 1)$, where “n” is an odd integer. The two clocks are set to $f_{\rm cpu}/(n+1)$ and $f_{\rm cpu}/(n-1)$.
• The low-pass filter design is also parametrized by “n”. If we define passband at the triangle’s 5th harmonic, then non dimensional value (f_stop / f_pass), representing the transition band, comes out to n/5.
• The non dimensional transition band corresponds to "filter complexity". A narrower transition band places more demands on the filter design. Given a lower limit of this value, the practical upper limit for the triangle frequency can then be derived relative to f_cpu, as $$\frac{2 f_{\rm pass}^2}{25 f_{\rm stop}^2}.$$
• Typical values shown below.
• ----
• Practical limit of f_triangle
• | min acceptable (f_stop / f_pass) | max (f_triangle / f_cpu) |
• |- | - |
• | 20 | 1 / 5000 |
• | 40 | 1 / 20000 |
• | 60 (recommended) | 1 / 45000 |
• | 80 | 1 / 80000 |
• | 100 | 1 / 125000 |
• -----
• Example Circuit producing 199Hz from 10MHz f_cpu
• 
• Simulation of above circuit. 0-1V inputs produce 12mV - 988 mV peaks
• 
• Detail showing less than 1% ripple.
• 
• -----
• Additional details of the analysis, and example showing the design calculation, are [here (pdf file, 5 pages)](https://gofile.io/d/hMXWWc). The site format is a little limiting unfortunately.

microcontroller PWM waveform-generation triangle-wave

#1: Post edited by Pete W‭ · 2020-12-30T17:12:24Z (over 3 years ago)

Raw

Markdown

• What follows is a proposed concept of a simple (in principle!) way to generate a fixed-amplitude triangle wave, using two clocks, an XOR gate, and not using any processor cycles.
• It is practical in the low-mid-100-Hz ballpark, with typical mcu clocks. Motivating application is dither waveform for solenoid valve control signals.
• ----
• SUMMARY
• Two timers output two clocks A, B, with fixed 50% duty cycle. XOR(A,B) produces a symmetrical PWM triangle wave, with modulation frequency at (f_A + f_B), and triangle frequency at (f_A - f_B). No other additional hardware. Illustrated below -- the resulting waveform on the bottom is a PWM. (click to zoom)
• [
• ](https://electrical.codidact.com/uploads/6bdrMJQBbLLbZvD8EJo2Fq1L)
• Given a master clock f_cpu, the available triangle frequencies are 2 * f_cpu / (n^2 - 1), where “n” is an odd integer. The two clocks are set to f_cpu/(n+1) and f_cpu/(n-1).
• The low-pass filter design is also parametrized by “n”. If we define passband at the triangle’s 5th harmonic, then nondimensional value (f_stop / f_pass), representing the transition band, comes out to n/5.
• The nondimensional transition band corresponds to "filter complexity". A narrower transition band places more demands on the filter design. Given a lower limit of this value, the practical upper limit for the triangle frequency can then be derived relative to f_cpu, as (2/25)/(f_stop/f_pass)^2 . Typical values shown below.
• ----
• Practical limit of f_triangle
• | min acceptable (f_stop / f_pass) | max (f_triangle / f_cpu) |
• |- | - |
• | 20 | 1 / 5000 |
• | 40 | 1 / 20000 |
• | 60 (recommended) | 1 / 45000 |
• | 80 | 1 / 80000 |
• | 100 | 1 / 125000 |
• -----
• Example Circuit producing 199Hz from 10MHz f_cpu
• 
• Simulation of above circuit. 0-1V inputs produce 12mV - 988 mV peaks
• 
• Detail showing less than 1% ripple.
• 
• -----
• Additional details of the analysis, and example showing the design calculation, are [here (pdf file, 5 pages)](https://gofile.io/d/hMXWWc). The site format is a little limiting unfortunately.

• What follows is a proposed concept of a simple (in principle!) way to generate a fixed-amplitude triangle wave, using two clocks, an XOR gate, and not using any processor cycles.
• It is practical in the low-mid-100-Hz ballpark, with typical mcu clocks. Motivating application is dither waveform for solenoid valve control signals.
• ----
• SUMMARY
• Two timers output two clocks A, B, with fixed 50% duty cycle. XOR(A,B) produces a symmetrical PWM triangle wave, with modulation frequency at (f_A + f_B), and triangle frequency at (f_A - f_B). No other additional hardware. Illustrated below -- the resulting waveform on the bottom is a PWM. (click to zoom)
• [
• ](https://electrical.codidact.com/uploads/6bdrMJQBbLLbZvD8EJo2Fq1L)
• Given a master clock f_cpu, the available triangle frequencies are 2 * f_cpu / (n^2 - 1), where “n” is an odd integer. The two clocks are set to f_cpu/(n+1) and f_cpu/(n-1).
• The low-pass filter design is also parametrized by “n”. If we define passband at the triangle’s 5th harmonic, then nondimensional value (f_stop / f_pass), representing the transition band, comes out to n/5.
• The nondimensional transition band corresponds to "filter complexity". A narrower transition band places more demands on the filter design. Given a lower limit of this value, the practical upper limit for the triangle frequency can then be derived relative to f_cpu, as (2/25)/(f_stop/f_pass)^2 . Typical values shown below.
• ----
• Practical limit of f_triangle
• | min acceptable (f_stop / f_pass) | max (f_triangle / f_cpu) |
• |- | - |
• | 20 | 1 / 5000 |
• | 40 | 1 / 20000 |
• | 60 (recommended) | 1 / 45000 |
• | 80 | 1 / 80000 |
• | 100 | 1 / 125000 |
• -----
• Example Circuit producing 199Hz from 10MHz f_cpu
• 
• Simulation of above circuit. 0-1V inputs produce 12mV - 988 mV peaks
• 
• Detail showing less than 1% ripple.
• 
• -----
• Additional details of the analysis, and example showing the design calculation, are [here (pdf file, 5 pages)](https://gofile.io/d/hMXWWc). I don't know this site's markup features well enough yet to get it the local format easily...