Post History
I am working on routing a microprocessor to two identical single data rate (SDR) SDRAM chips that are PC166 compliant, particularly Alliance AS4C16M16SB-6TIN. The 16 bit SDRAM chips are combined t...
#3: Post edited
by
Lorenzo Donati
·
2023-08-10T12:14:34Z (over 1 year ago)
#2: Post edited
by
DavidE
·
2023-05-30T04:32:05Z (over 1 year ago)
I am working on routing a microprocessor to two identical single data rate (SDR) SDRAM chips that are PC166 compliant, particularly Alliance AS4C16M16SB-6TIN. The 16 bit SDRAM chips are combined to form a 32 bit word. The microprocessor is of the NXP i.MX RT1170 family and has an external memory controller that supports PC166. How can one use the data sheets for both parts to determine PCB routing requirements such as length matching between particular nets and the maximum length any net can be? In other words how do you use the data sheets to determine a timing budget for the PCB interconnect?
- I am working on routing a microprocessor to two identical single data rate (SDR) SDRAM chips that are PC166 compliant, particularly Alliance [AS4C16M16SB-6TIN](https://www.alliancememory.com/wp-content/uploads/pdf/dram/AllianceMemory_256M_SDRAM_Bdie_AS4C16M16SB-xBIN_TIN(TCN)_25June2021_Rev2.0.pdf). The 16 bit SDRAM chips are combined to form a 32 bit word. The microprocessor is of the NXP [i.MX RT1170](https://www.nxp.com/docs/en/nxp/data-sheets/IMXRT1170IEC.pdf) family and has an external memory controller that supports PC166. How can one use the data sheets for both parts to determine PCB routing requirements such as length matching between particular nets and the maximum length any net can be? In other words how do you use the data sheets to determine a timing budget for the PCB interconnect?
- Based on Olin's great response I added the links for the data sheets (above) and below I attempt at determining the timing requirements. I would appreciate any feedback on the analysis.
- **Processor Output, Memory Input Direction**:
- Page 21 of the memory data sheet states that the chip has a minimum Data/Address/Control Input set-up time of 1.5ns, and a minimum Data/Address/Control Input hold time of 0.8ns. Thus the data, address, and control signals need to be at the chips pin for at least 2.3ns.
- Page 62 of the processor data sheet states that the chip has a maximum Data Output Valid time of 0.6ns and a minimum data output hold time of -0.7ns. So if I understand correctly, assuming a 167MHz clock, which is a period of 5.99ns, the valid data arrives at 5.99ns/2 - 0.6ns = 2.40ns before the positive clock edge and remains valid for 5.99ns/2 + -0.7ns = 2.30ns after the positive clock edge. Thus the output window is 2.40ns + 2.30ns = 4.70ns.
- Luckily the processor output window exceeds the minimum memory input window. Further, the clock does not need to be skewed because the memory input setup and hold times are met individually too. The margin for the setup time is 2.40ns - 1.5ns = 0.9ns. The margin for the hold time is 2.3ns - 0.8ns = 1.5ns.
- **Processor Input, Memory Output Direction**:
- Page 64 of the processor data sheet states that the chip has a minimum data input setup of 0.6ns, and a minimum data input hold of 1ns. Thus the total window required is 0.6ns + 1ns = 1.6ns.
- Page 21 of the memory data sheet states that the chip has a minimum access time from positive clock edge of 6ns or 5ns for a CAS latency setting of 2 or 3 clock cycles respectively. The chips has a minimum data output hold time of 2.5ns. Assuming a 167MHz clock again (5.99ns period), the data output from the memory chip is 0.01ns after the positive clock edge, or 0.99ns before the positive clock edge (where the clock edge is the clock that the memory chip sees). The total output window is either -0.01ns + 2.5ns = 2.49ns or 0.99ns + 2.5ns + 3.49ns for the CAS latency of 2 and 3 respectively.
- Thus both options meet the total window required by the processor. However, assuming there was no propagation delay between the processor and memory, only the latter case (CAS latency of 3) meets the setup time requirement in addition to the hold requirement. The margin for the case of CAS latency of 3 is 0.99ns - 0.6ns = 0.33ns for the setup time, and 2.5ns - 1ns = 1.5ns for the hold time.
- **Accounting for Propogation Delay:**
- The previous analysis showed that the smallest margin of both directions of operation is 0.33ns, which is the case for when the processor is reading from memory. Assuming the propogation speed on the PCB is 6in/ns, then the trace lengths between the processor and the memory chip need to be less than (0.33ns/2)*(6in/ns) = 0.99 in. This maximum distance does not seem feasible (the SDRAM chip package is large). So I think that if I want to use this memory chip, I will need to run it at a slower clock, perhaps 143MHz.
- Is the above analysis valid?
#1: Initial revision
by
DavidE
·
2023-05-26T00:23:12Z (over 1 year ago)
SDR SDRAM PCB Timing Budget
I am working on routing a microprocessor to two identical single data rate (SDR) SDRAM chips that are PC166 compliant, particularly Alliance AS4C16M16SB-6TIN. The 16 bit SDRAM chips are combined to form a 32 bit word. The microprocessor is of the NXP i.MX RT1170 family and has an external memory controller that supports PC166. How can one use the data sheets for both parts to determine PCB routing requirements such as length matching between particular nets and the maximum length any net can be? In other words how do you use the data sheets to determine a timing budget for the PCB interconnect?